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ICacheCntrl now reacts differently to InstrPageFaultF vs ITLBWriteF

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bbracker 2021-07-04 18:17:06 -04:00
parent 7191c03282
commit ceac0352f7
1 changed files with 11 additions and 4 deletions
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15
wally-pipelined/src/cache/ICacheCntrl.sv vendored
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@ -115,8 +115,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
localparam STATE_INVALIDATE = 'h12; // *** not sure if invalidate or evict? invalidate by cache block or address? localparam STATE_INVALIDATE = 'h12; // *** not sure if invalidate or evict? invalidate by cache block or address?
localparam STATE_TLB_MISS = 'h13; localparam STATE_TLB_MISS = 'h13;
localparam STATE_TLB_MISS_DONE = 'h14; localparam STATE_TLB_MISS_DONE = 'h14;
localparam STATE_INSTR_PAGE_FAULT = 'h15;
localparam AHBByteLength = `XLEN / 8; localparam AHBByteLength = `XLEN / 8;
localparam AHBOFFETWIDTH = $clog2(AHBByteLength); localparam AHBOFFETWIDTH = $clog2(AHBByteLength);
@ -370,13 +370,20 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
NextState = STATE_READY; NextState = STATE_READY;
end end
STATE_TLB_MISS: begin STATE_TLB_MISS: begin
if (ITLBWriteF | WalkerInstrPageFaultF) begin if (WalkerInstrPageFaultF) begin
NextState = STATE_INSTR_PAGE_FAULT;
ICacheStallF = 1'b0;
end else if (ITLBWriteF) begin
NextState = STATE_TLB_MISS_DONE; NextState = STATE_TLB_MISS_DONE;
end else begin end else begin
NextState = STATE_TLB_MISS; NextState = STATE_TLB_MISS;
end end
end end
STATE_TLB_MISS_DONE : begin STATE_TLB_MISS_DONE: begin
NextState = STATE_READY;
end
STATE_INSTR_PAGE_FAULT: begin
ICacheStallF = 1'b0;
NextState = STATE_READY; NextState = STATE_READY;
end end
default: begin default: begin