Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

wally-pipelined/regression/wave.do

@@ -2,51 +2,53 @@ onerror {resume}
 quietly WaveActivateNextPane {} 0
 add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
+add wave -noupdate /testbench/test
+add wave -noupdate /testbench/memfilename
 add wave -noupdate /testbench/dut/hart/SATP_REGW
+add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
 add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
 add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
 add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
-add wave -noupdate -expand -group {Memory Stage} /testbench/PCtextM
 add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
+add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
+add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
+add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
+add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
 add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
 add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
 add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
@@ -114,19 +116,19 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
-add wave -noupdate -expand -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
+add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
-add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
-add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
-add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
-add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
-add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
@@ -248,31 +250,53 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUIn
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/WayIn
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/NewLRUEn
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUOut
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/VictimWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/ReplacementBits
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/LRUWriteEn
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/WriteWordEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/StoredData}
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockSetsM
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/FinalReadDataWordM
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/BlockReplacementBits
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
@@ -282,7 +306,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victi
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataWEn
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
@@ -328,7 +351,7 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM
 add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
 add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
 add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -divider data
+add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
 add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
 add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
 add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
@@ -396,15 +419,14 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb
 add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
 add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
 add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
-add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/Address
 add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HCLK
 add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HSELUART
 add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR
 add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE
 add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {5126 ns} 0} {{Cursor 2} {203758 ns} 0} {{Cursor 3} {6427 ns} 0}
+WaveRestoreCursors {{Walk read is wrong} {26824 ns} 1} {{page table setup} {8167 ns} 1} {{eviction at wrong adr} {10128 ns} 1} {{Cursor 6} {9967 ns} 0}
-quietly wave cursor active 2
+quietly wave cursor active 4
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 297
 configure wave -justifyvalue left
@@ -419,4 +441,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {203677 ns} {203893 ns}
+WaveRestoreZoom {9904 ns} {10352 ns}

wally-pipelined/src/cache/cacheLRU.sv

@@ -0,0 +1,81 @@
+///////////////////////////////////////////
+// dcache (data cache)
+//
+// Written: ross1728@gmail.com July 20, 2021
+//          Implements Pseudo LRU
+//
+//
+// A component of the Wally configurable RISC-V project.
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module cacheLRU
+  #(NUMWAYS)
+  (input logic [NUMWAYS-2:0] LRUIn,
+   input logic [NUMWAYS-1:0] WayIn,
+   output logic [NUMWAYS-2:0] LRUOut,
+   output logic [NUMWAYS-1:0] VictimWay
+   );
+
+  //  *** Only implements 2, 4, and 8 way
+  // I would like parametersize this in the future.
+
+  logic [NUMWAYS-2:0] 	      LRUEn, LRUMask;
+  logic [$clog2(NUMWAYS)-1:0] EncVicWay;
+
+  genvar 		      index;
+  generate
+    if(NUMWAYS == 2) begin : TwoWay
+      
+      assign LRUEn[0] = 1'b0;
+
+      assign LRUOut[0] = WayIn[1];
+
+      assign VictimWay[1] = ~LRUIn[0];
+      assign VictimWay[0] = LRUIn[0];
+      
+    end else if (NUMWAYS == 4) begin : FourWay 
+
+      // selects
+      assign LRUEn[2] = 1'b1;
+      assign LRUEn[1] = WayIn[3];      
+      assign LRUEn[0] = WayIn[3] | WayIn[2];
+
+      // mask
+      assign LRUMask[0] = WayIn[1];
+      assign LRUMask[1] = WayIn[3];      
+      assign LRUMask[2] = WayIn[3] | WayIn[2];
+
+      for(index = 0; index < NUMWAYS-1; index++)
+	assign LRUOut[index] = LRUEn[index] ? LRUIn[index] : LRUMask[index];
+
+      assign EncVicWay[1] = LRUIn[2];
+      assign EncVicWay[0] = LRUIn[2] ? LRUIn[0] : LRUIn[1];
+
+      oneHotDecoder #(2) 
+      oneHotDecoder(.bin(EncVicWay),
+		    .decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3]}));
+
+    end else if (NUMWAYS == 8) begin : EightWay
+
+    end
+  endgenerate
+  
+endmodule
+
+  

wally-pipelined/src/cache/dcache.sv

@@ -38,8 +38,9 @@ module dcache
    input logic [2:0] 	       Funct3M,
    input logic [6:0] 	       Funct7M,
    input logic [1:0] 	       AtomicM,
-   input logic [`XLEN-1:0]     MemAdrE, // virtual address, but we only use the lower 12 bits.
+   input logic [11:0] 	       MemAdrE, // virtual address, but we only use the lower 12 bits.
    input logic [`PA_BITS-1:0]  MemPAdrM, // physical address
+   input logic [11:0]          VAdr, // when hptw writes dtlb we use this address to index SRAM.
 
    input logic [`XLEN-1:0]     WriteDataM,
    output logic [`XLEN-1:0]    ReadDataW,
@@ -98,8 +99,9 @@ module dcache
   logic [TAGLEN-1:0]	       ReadTag [NUMWAYS-1:0];
   logic [NUMWAYS-1:0]	       Valid, Dirty, WayHit;
   logic			       CacheHit;
-  logic [NUMREPL_BITS-1:0]     ReplacementBits [NUMLINES-1:0];
+  logic [NUMWAYS-2:0] 	       ReplacementBits [NUMLINES-1:0];
-  logic [NUMREPL_BITS-1:0]     NewReplacement;
+  logic [NUMWAYS-2:0] 	       BlockReplacementBits;
+  logic [NUMWAYS-2:0] 	       NewReplacement;
   logic [BLOCKLEN-1:0]	       ReadDataBlockM;
   logic [`XLEN-1:0]	       ReadDataBlockSetsM [(WORDSPERLINE)-1:0];
   logic [`XLEN-1:0]	       VictimReadDataBlockSetsM [(WORDSPERLINE)-1:0];  
@@ -113,6 +115,7 @@ module dcache
 
   logic 		       SRAMWordWriteEnableM, SRAMWordWriteEnableW;
   logic 		       SRAMBlockWriteEnableM;
+  logic [NUMWAYS-1:0] 	       SRAMBlockWayWriteEnableM;
   logic 		       SRAMWriteEnable;
   logic [NUMWAYS-1:0] 	       SRAMWayWriteEnable;
   
@@ -142,7 +145,8 @@ module dcache
   logic CntReset;
   logic CPUBusy, PreviousCPUBusy;
   logic SelEvict;
-  
+
+  logic LRUWriteEn;
   
   typedef enum {STATE_READY,
 
@@ -197,10 +201,11 @@ module dcache
 
   // data path
 
-  mux2 #(INDEXLEN)
+  mux3 #(INDEXLEN)
   AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	    .d1(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
-	    .s(SelAdrM),
+	    .d2(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
+	    .s({DTLBWriteM, SelAdrM}),
 	    .y(SRAMAdr));
 
 
@@ -222,7 +227,7 @@ module dcache
 	     .WAdr(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	     .WriteEnable(SRAMWayWriteEnable[way]),
 	     .WriteWordEnable(SRAMWordEnable),
-	     .TagWriteEnable(SRAMBlockWriteEnableM),
+	     .TagWriteEnable(SRAMBlockWayWriteEnableM[way]), 
 	     .WriteData(SRAMWriteData),
 	     .WriteTag(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
 	     .SetValid(SetValidM),
@@ -234,32 +239,51 @@ module dcache
 	     .Valid(Valid[way]),
 	     .Dirty(Dirty[way]));
       assign WayHit[way] = Valid[way] & (ReadTag[way] == MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
-      assign ReadDataBlockWayMaskedM[way] = Valid[way] ? ReadDataBlockWayM[way] : '0;  // first part of AO mux.
+      assign ReadDataBlockWayMaskedM[way] = WayHit[way] ? ReadDataBlockWayM[way] : '0;  // first part of AO mux.
 
       // the cache block candiate for eviction
       // *** this should be sharable with the read data muxing, but for now i'm doing the simple
       // thing and making them separate.
       assign VictimReadDataBLockWayMaskedM[way] = VictimWay[way] ? ReadDataBlockWayM[way] : '0;
       assign VictimDirtyWay[way] = VictimWay[way] & Dirty[way] & Valid[way];
-      assign VictimTagWay[way] = Valid[way] ? ReadTag[way] : '0;
+      assign VictimTagWay[way] = VictimWay[way] ? ReadTag[way] : '0;
     end
   endgenerate
 
   always_ff @(posedge clk, posedge reset) begin
     if (reset) begin
-      for(int index = 0; index < NUMLINES-1; index++)
+      for(int index = 0; index < NUMLINES; index++)
 	ReplacementBits[index] <= '0;
+    end else begin
+      BlockReplacementBits <= ReplacementBits[SRAMAdr];
+      if (LRUWriteEn) begin
+	ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement;
+      end
     end
-    else if (SRAMWriteEnable) ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement;
   end
 
-  // *** TODO add replacement policy
+  // *** TODO only supports 1, 2, 4, and 8 way
-  assign NewReplacement = '0;
+  generate
-  assign VictimWay = 4'b0001;
+    if(NUMWAYS > 1) begin
+      cacheLRU #(NUMWAYS)
+      cacheLRU(.LRUIn(BlockReplacementBits),
+	       .WayIn(WayHit),
+	       .LRUOut(NewReplacement),
+	       .VictimWay(VictimWay));
+    end else begin
+      assign NewReplacement = '0;
+      assign VictimWay = 1'b1;
+    end
+  endgenerate
+
+  assign SRAMBlockWayWriteEnableM = SRAMBlockWriteEnableM ? VictimWay : '0;
+  
   mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0),
-				 .d1(SRAMBlockWriteEnableM ? VictimWay : '0),
+				 .d1(SRAMBlockWayWriteEnableM),
 				 .s(SRAMBlockWriteEnableM),
 				 .y(SRAMWayWriteEnable));
+
+  
   
   
 
@@ -283,6 +307,7 @@ module dcache
 
   // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can
   // easily build a variable input mux.
+  // *** consider using a limited range shift to do this final muxing.
   generate
     for (index = 0; index < WORDSPERLINE; index++) begin
       assign ReadDataBlockSetsM[index] = ReadDataBlockM[((index+1)*`XLEN)-1: (index*`XLEN)];
@@ -444,6 +469,7 @@ module dcache
     SelEvict = 1'b0;
     DCacheAccess = 1'b0;
     DCacheMiss = 1'b0;
+    LRUWriteEn = 1'b0;
 
     case (CurrState)
       STATE_READY: begin
@@ -480,6 +506,7 @@ module dcache
 	else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
 	  DCacheStall = 1'b0;
 	  DCacheAccess = 1'b1;
+	  LRUWriteEn = 1'b1;
 	  
 	  if(StallW) begin
 	    NextState = STATE_CPU_BUSY;
@@ -494,6 +521,7 @@ module dcache
 	  SRAMWordWriteEnableM = 1'b1;
 	  SetDirtyM = 1'b1;
 	  DCacheStall = 1'b1;
+	  LRUWriteEn = 1'b1;
 	  
 	  if(StallW) begin 
 	    NextState = STATE_CPU_BUSY;
@@ -578,6 +606,7 @@ module dcache
 	SetValidM = 1'b1;
 	ClearDirtyM = 1'b1;
 	CommittedM = 1'b1;
+	//LRUWriteEn = 1'b1;  // DO not update LRU on SRAM fetch update.  Wait for subsequent read/write
       end
 
       STATE_MISS_READ_WORD: begin
@@ -596,6 +625,7 @@ module dcache
       STATE_MISS_READ_WORD_DELAY: begin
 	//SelAdrM = 1'b1;
 	CommittedM = 1'b1;
+	LRUWriteEn = 1'b1;
 	if(StallW) begin 
 	  NextState = STATE_CPU_BUSY;
 	  SelAdrM = 1'b1;
@@ -609,6 +639,7 @@ module dcache
 	SelAdrM = 1'b1;
 	DCacheStall = 1'b1;
 	CommittedM = 1'b1;
+	LRUWriteEn = 1'b1;
 	NextState = STATE_MISS_WRITE_WORD_DELAY;
       end
 
@@ -658,6 +689,7 @@ module dcache
 	end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin
 	  NextState = STATE_PTW_READY;
 	  DCacheStall = 1'b0;
+	  LRUWriteEn = 1'b1;
 	end
 
 	// read miss valid cached
@@ -724,6 +756,7 @@ module dcache
 	SetValidM = 1'b1;
 	ClearDirtyM = 1'b1;
 	CommittedM = 1'b1;
+	//LRUWriteEn = 1'b1;
       end
 
       STATE_PTW_READ_MISS_READ_WORD: begin
@@ -743,6 +776,7 @@ module dcache
 	DCacheStall = 1'b1;
 	SelAdrM = 1'b1;
 	CommittedM = 1'b1;
+	LRUWriteEn = 1'b1;
 	NextState = STATE_READY;
       end
       

wally-pipelined/src/fpu/fpu.sv

@@ -204,7 +204,7 @@ module fpu (
 	fpdiv fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .done(FDivSqrtDoneE), .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]), 
 			.P(~FmtE), .FDivBusyE, .HoldInputs, 
 			.OvEn(1'b1), .UnEn(1'b1),
-			.start(FDivStartE), .reset, .clk(~clk), .AS_Result(FDivResultM), .Flags(FDivSqrtFlgM));
+			.start(FDivStartE), .reset, .clk(fpdivClk), .AS_Result(FDivResultM), .Flags(FDivSqrtFlgM));
 	
         // .DivOpType(FOpCtrlE[0]), .clk(fpdivClk), .FmtE(~FmtE), .DivInput1E, .DivInput2E, 
         //                 .FrmE, .DivOvEn(1'b1), .DivUnEn(1'b1), .FDivStartE, .FDivResultM, .FDivSqrtFlgM, 

wally-pipelined/src/fpu/fsm.sv

@@ -476,7 +476,7 @@ module fsm (done, load_rega, load_regb, load_regc,
 	       sel_muxa = 3'b011;
 	       sel_muxb = 3'b110;
 	       sel_muxr = 1'b1;
-	       NEXT_STATE = S27;
+	       NEXT_STATE = S26;
 	    end 
 	  S26:  // done
 	    begin

wally-pipelined/src/ifu/ifu.sv

@@ -98,10 +98,9 @@ module ifu (
   logic 	    reset_q; // *** look at this later.
 
   logic 	    BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
-
-  logic 	    PMPInstrAccessFaultF, PMAInstrAccessFaultF;
   
-  logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width. 
+  logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
+  logic [`XLEN+1:0]    PCFExt;
 
   generate
     if (`XLEN==32) begin
@@ -113,8 +112,10 @@ module ifu (
     end
   endgenerate
 
+  assign PCFExt = {2'b00, PCF};
   mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
-  immu(.Address(PCF),
+  immu(.PAdr(PCFExt[`PA_BITS-1:0]),
+       .VAdr(PCF),
        .Size(2'b10),
        .PTE(PTE),
        .PageTypeWriteVal(PageType),

wally-pipelined/src/lsu/lsu.sv

@@ -125,16 +125,14 @@ module lsu
   logic 		       HPTWStall;  
   logic [`XLEN-1:0] 	       HPTWPAdrE;
 //  logic [`XLEN-1:0] 	       HPTWPAdrM;  
-  logic [`XLEN-1:0] TranslationVAdr;
   logic [`PA_BITS-1:0] TranslationPAdr;
-  logic            UseTranslationVAdr;
   logic 		       HPTWRead;
   logic [1:0] 		       MemRWMtoDCache;
   logic [1:0] 		       MemRWMtoLRSC;
   logic [2:0] 		       Funct3MtoDCache;
   logic [1:0] 		       AtomicMtoDCache;
-  logic [`XLEN-1:0] 	       MemAdrMtoDCache;
+  logic [`PA_BITS-1:0] 	       MemPAdrMtoDCache;
-  logic [`XLEN-1:0] 	       MemAdrEtoDCache;  
+  logic [11:0] 		       MemAdrEtoDCache;  
   logic [`XLEN-1:0] 	       ReadDataWfromDCache;
   logic 		       StallWtoDCache;
   logic            MemReadM;
@@ -154,35 +152,27 @@ module lsu
   
   
   hptw hptw(
-				  .clk(clk),
+	    .clk(clk),
-				  .reset(reset),
+	    .reset(reset),
-				  .SATP_REGW(SATP_REGW),
+	    .SATP_REGW(SATP_REGW),
-				  .PCF(PCF),
+	    .PCF(PCF),
-				  .MemAdrM(MemAdrM),
+	    .MemAdrM(MemAdrM),
-				  .ITLBMissF(ITLBMissF),
+	    .ITLBMissF(ITLBMissF),
-				  .DTLBMissM(DTLBMissM),
+	    .DTLBMissM(DTLBMissM),
-				  .MemRWM(MemRWM),
+	    .MemRWM(MemRWM),
-				  .PTE(PTE),
+	    .PTE(PTE),
-				  .PageType,
+	    .PageType,
-				  .ITLBWriteF(ITLBWriteF),
+	    .ITLBWriteF(ITLBWriteF),
-				  .DTLBWriteM(DTLBWriteM),
+	    .DTLBWriteM(DTLBWriteM),
-				  .HPTWReadPTE(HPTWReadPTE),
+	    .HPTWReadPTE(HPTWReadPTE),
-				  .HPTWStall(HPTWStall),
+	    .HPTWStall(HPTWStall),
-          .TranslationVAdr,
+            .TranslationPAdr,			  
-          .TranslationPAdr,			  
+	    .HPTWRead(HPTWRead),
-          .UseTranslationVAdr,
+	    .SelPTW(SelPTW),
-				  .HPTWRead(HPTWRead),
+	    .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
-				  .SelPTW(SelPTW),
+	    .WalkerLoadPageFaultM(WalkerLoadPageFaultM),  
-				  .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
+	    .WalkerStorePageFaultM(WalkerStorePageFaultM));
-				  .WalkerLoadPageFaultM(WalkerLoadPageFaultM),  
-				  .WalkerStorePageFaultM(WalkerStorePageFaultM));
 
-  logic [`XLEN-1:0] TranslationPAdrXLEN;
-  generate // *** needs fixing about truncation dh 7/17/21
-    if (`XLEN == 32) assign TranslationPAdrXLEN = TranslationPAdr[31:0];
-    else             assign TranslationPAdrXLEN = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
-  endgenerate
-  mux2 #(`XLEN) HPTWPAdrMux(TranslationPAdrXLEN, TranslationVAdr, UseTranslationVAdr, HPTWPAdrE); // *** misleading to call it PAdr, bad because some bits have been truncated
   
   assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
 
@@ -192,7 +182,7 @@ module lsu
 		 // HPTW connection
 		 .SelPTW(SelPTW),
 		 .HPTWRead(HPTWRead),
-		 .HPTWPAdrE(HPTWPAdrE),
+		 .TranslationPAdrE(TranslationPAdr),
 		 .HPTWStall(HPTWStall),		 
 		 // CPU connection
 		 .MemRWM(MemRWM),
@@ -211,7 +201,7 @@ module lsu
 		 .MemRWMtoLRSC(MemRWMtoLRSC),
 		 .Funct3MtoDCache(Funct3MtoDCache),
 		 .AtomicMtoDCache(AtomicMtoDCache),
-		 .MemAdrMtoDCache(MemAdrMtoDCache),
+		 .MemPAdrMtoDCache(MemPAdrMtoDCache),
 		 .MemAdrEtoDCache(MemAdrEtoDCache),
 		 .StallWtoDCache(StallWtoDCache),
 		 .DataMisalignedMfromDCache(DataMisalignedMfromDCache),
@@ -224,7 +214,8 @@ module lsu
     
   
   mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
-  dmmu(.Address(MemAdrMtoDCache),
+  dmmu(.PAdr(MemPAdrMtoDCache),
+       .VAdr(MemAdrM),
        .Size(Funct3MtoDCache[1:0]),
        .PTE(PTE),
        .PageTypeWriteVal(PageType),
@@ -269,9 +260,9 @@ module lsu
   always_comb
     case(Funct3MtoDCache[1:0]) 
       2'b00:  DataMisalignedMfromDCache = 0;                       // lb, sb, lbu
-      2'b01:  DataMisalignedMfromDCache = MemAdrMtoDCache[0];              // lh, sh, lhu
+      2'b01:  DataMisalignedMfromDCache = MemPAdrMtoDCache[0];              // lh, sh, lhu
-      2'b10:  DataMisalignedMfromDCache = MemAdrMtoDCache[1] | MemAdrMtoDCache[0]; // lw, sw, flw, fsw, lwu
+      2'b10:  DataMisalignedMfromDCache = MemPAdrMtoDCache[1] | MemPAdrMtoDCache[0]; // lw, sw, flw, fsw, lwu
-      2'b11:  DataMisalignedMfromDCache = |MemAdrMtoDCache[2:0];           // ld, sd, fld, fsd
+      2'b11:  DataMisalignedMfromDCache = |MemPAdrMtoDCache[2:0];           // ld, sd, fld, fsd
     endcase 
 
   // Squash unaligned data accesses and failed store conditionals
@@ -312,6 +303,7 @@ module lsu
 		.AtomicM(AtomicMtoDCache),
 		.MemAdrE(MemAdrEtoDCache),
 		.MemPAdrM(MemPAdrM),
+		.VAdr(MemAdrM[11:0]),		
 		.WriteDataM(WriteDataM),
 		.ReadDataW(ReadDataWfromDCache),
 		.ReadDataM(HPTWReadPTE),

wally-pipelined/src/lsu/lsuArb.sv

@@ -30,46 +30,47 @@ module lsuArb
   (input  logic clk, reset,
 
    // from page table walker
-   input logic 		    SelPTW,
+   input logic 		       SelPTW,
-   input logic 		    HPTWRead,
+   input logic 		       HPTWRead,
-   input logic [`XLEN-1:0]  HPTWPAdrE,
+   input logic [`PA_BITS-1:0]  TranslationPAdrE,
-   output logic 	    HPTWStall, 
+   output logic 	       HPTWStall, 
 
    // from CPU
-   input logic [1:0] 	    MemRWM,
+   input logic [1:0] 	       MemRWM,
-   input logic [2:0] 	    Funct3M,
+   input logic [2:0] 	       Funct3M,
-   input logic [1:0] 	    AtomicM,
+   input logic [1:0] 	       AtomicM,
-   input logic [`XLEN-1:0]  MemAdrM,
+   input logic [`XLEN-1:0]     MemAdrM,
-   input logic [`XLEN-1:0]  MemAdrE,
+   input logic [`XLEN-1:0]     MemAdrE,
-   input logic 		    StallW,
+   input logic 		       StallW,
-   input logic 		    PendingInterruptM,
+   input logic 		       PendingInterruptM,
    // to CPU
-   output logic [`XLEN-1:0] ReadDataW,
+   output logic [`XLEN-1:0]    ReadDataW,
-   output logic 	    DataMisalignedM,
+   output logic 	       DataMisalignedM,
-   output logic 	    CommittedM,
+   output logic 	       CommittedM,
-   output logic 	    LSUStall, 
+   output logic 	       LSUStall, 
   
    // to D Cache
-   output logic 	    DisableTranslation, 
+   output logic 	       DisableTranslation, 
-   output logic [1:0] 	    MemRWMtoLRSC,
+   output logic [1:0] 	       MemRWMtoLRSC,
-   output logic [2:0] 	    Funct3MtoDCache,
+   output logic [2:0] 	       Funct3MtoDCache,
-   output logic [1:0] 	    AtomicMtoDCache,
+   output logic [1:0] 	       AtomicMtoDCache,
-   output logic [`XLEN-1:0] MemAdrMtoDCache,
+   output logic [`PA_BITS-1:0] MemPAdrMtoDCache,
-   output logic [`XLEN-1:0] MemAdrEtoDCache, 
+   output logic [11:0] 	       MemAdrEtoDCache, 
-   output logic 	    StallWtoDCache,
+   output logic 	       StallWtoDCache,
-   output logic 	    PendingInterruptMtoDCache,
+   output logic 	       PendingInterruptMtoDCache,
    
 
    // from D Cache
-   input logic 		    CommittedMfromDCache,
+   input logic 		       CommittedMfromDCache,
-   input logic 		    DataMisalignedMfromDCache,
+   input logic 		       DataMisalignedMfromDCache,
-   input logic [`XLEN-1:0]  ReadDataWfromDCache,
+   input logic [`XLEN-1:0]     ReadDataWfromDCache,
-   input logic 		    DCacheStall
+   input logic 		       DCacheStall
   
    );
 
   logic [2:0] PTWSize;
-  logic [`XLEN-1:0]  HPTWPAdrM;
+  logic [`PA_BITS-1:0]  TranslationPAdrM;
+  logic [`XLEN+1:0]  MemAdrMExt;
   
   // multiplex the outputs to LSU
   assign DisableTranslation = SelPTW;  // change names between SelPTW would be confusing in DTLB.
@@ -80,11 +81,13 @@ module lsuArb
   endgenerate
   mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache);
 
-  flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM);   // delay HPTWPAdr by a cycle
+  // this is for the d cache SRAM.
+  flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdrE, TranslationPAdrM);   // delay TranslationPAdrM by a cycle
 
   assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
-  assign MemAdrMtoDCache = SelPTW ? HPTWPAdrM : MemAdrM; // *** DH: I don't understand this logic 7/18/21.  Why should PCF ever go here? 
+  assign MemAdrMExt = {2'b00, MemAdrM};
-  assign MemAdrEtoDCache = SelPTW ? HPTWPAdrE : MemAdrE;  
+  assign MemPAdrMtoDCache = SelPTW ? TranslationPAdrM : MemAdrMExt[`PA_BITS-1:0]; 
+  assign MemAdrEtoDCache = SelPTW ? TranslationPAdrE[11:0] : MemAdrE[11:0];  
   assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
   // always block interrupts when using the hardware page table walker.
   assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;

wally-pipelined/src/mmu/hptw.sv

@@ -43,9 +43,7 @@ module hptw
    output logic [1:0]	    PageType, // page type to TLBs
    output logic		    ITLBWriteF, DTLBWriteM, // write TLB with new entry
    output logic 	    SelPTW, // LSU Arbiter should select signals from the PTW rather than from the IEU
-   output logic [`XLEN-1:0]		    TranslationVAdr,
    output logic [`PA_BITS-1:0]	    TranslationPAdr,
-   output logic                     UseTranslationVAdr,
    output logic		    HPTWRead, // HPTW requesting to read memory
    output logic		    WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
 );
@@ -64,6 +62,8 @@ module hptw
       logic			    PRegEn;
 	  logic [1:0]       NextPageType;
       logic [`SVMODE_BITS-1:0]	    SvMode;
+      logic [`XLEN-1:0] 	    TranslationVAdr;
+      
 
       typedef enum  {LEVEL0_SET_ADR, LEVEL0_READ, LEVEL0,
 				     LEVEL1_SET_ADR, LEVEL1_READ, LEVEL1,
@@ -101,7 +101,6 @@ module hptw
 	  assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT);
 	  assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
 	  assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
-	  assign UseTranslationVAdr = (NextWalkerState == LEAF) || (WalkerState == LEAF); // ***explain this logic
 
 	  // Raise faults.  DTLBMiss
 	  assign WalkerInstrPageFaultF = (WalkerState == FAULT) & ~DTLBWalk;
@@ -198,7 +197,7 @@ module hptw
     end else begin // No Virtual memory supported; tie HPTW outputs to 0
       assign HPTWRead = 0; assign SelPTW = 0;
       assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0;
-	  assign TranslationVAdr = 0; assign TranslationPAdr = 0; assign UseTranslationVAdr = 0;
+      assign TranslationPAdr = 0; 
     end
   endgenerate
 endmodule

wally-pipelined/src/mmu/mmu.sv

@@ -44,8 +44,16 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
   // 11 - TLB is accessed for both read and write
   input logic              DisableTranslation,
 
-  //  address input (could be virtual or physical)
+  // VAdr goes to the TLB only. Virtual if the TLB is active.
-  input logic  [`XLEN-1:0] Address,
+  // PAdr goes to address mux bypassing the TLB.  PAdr used when there is no translation.
+  // Comes from either the program address (instruction address or load/store address)
+  // or from the hardware pagetable walker.
+  // PAdr is intended to used as a phsycial address.  Discarded by the address mux when translation is
+  // performed.  
+  // PhysicalAddress is selected to be PAdr when no translation or the translated VAdr (TLBPAdr)
+  // when there is translation.
+  input logic  [`PA_BITS-1:0] PAdr,  // *** consider renaming this.
+  input logic  [`XLEN-1:0] VAdr,
   input logic  [1:0]       Size, // 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
 
   // Controls for writing a new entry to the TLB
@@ -77,7 +85,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
 );
 
   logic [`PA_BITS-1:0] TLBPAdr;
-  logic [`XLEN+1:0]    AddressExt;
   logic PMPSquashBusAccess, PMASquashBusAccess;
   // Translation lookaside buffer
 
@@ -95,7 +102,9 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
       assign WriteAccess = WriteAccessM;
       tlb #(.TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU)) 
         tlb(.SATP_MODE(SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]),
-            .SATP_ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]), .*);
+            .SATP_ASID(SATP_REGW[`ASID_BASE+`ASID_BITS-1:`ASID_BASE]),
+	    .VAdr,
+	    .*);
 
     end else begin // just pass address through as physical
       assign Translate = 0;
@@ -106,8 +115,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
   endgenerate
 
   // If translation is occuring, select translated physical address from TLB
-  assign AddressExt = {2'b00, Address}; // extend length of virtual address if necessary for RV32
+  mux2 #(`PA_BITS) addressmux(PAdr, TLBPAdr, Translate, PhysicalAddress);
-  mux2 #(`PA_BITS) addressmux(AddressExt[`PA_BITS-1:0], TLBPAdr, Translate, PhysicalAddress);
   
   ///////////////////////////////////////////
   // Check physical memory accesses

wally-pipelined/src/mmu/tlb.sv

@@ -70,7 +70,7 @@ module tlb #(parameter TLB_ENTRIES = 8,
   input logic              DisableTranslation,
 
   // address input before translation (could be physical or virtual)
-  input logic  [`XLEN-1:0] Address,
+  input logic  [`XLEN-1:0] VAdr,
 
   // Controls for writing a new entry to the TLB
   input logic  [`XLEN-1:0] PTE,
@@ -95,20 +95,18 @@ module tlb #(parameter TLB_ENTRIES = 8,
   // Sections of the virtual and physical addresses
   logic [`VPN_BITS-1:0] VPN;
   logic [`PPN_BITS-1:0] PPN;
-  logic [`XLEN+1:0]     AddressExt;
 
   // Sections of the page table entry
   logic [7:0]           PTEAccessBits;
   logic [11:0]          PageOffset;
 
-  logic                  PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits
   logic [1:0]            HitPageType;
   logic                  CAMHit;
   logic                  SV39Mode;
 
-  assign VPN = Address[`VPN_BITS+11:12];
+  assign VPN = VAdr[`VPN_BITS+11:12];
 
-  tlbcontrol tlbcontrol(.SATP_MODE, .Address, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+  tlbcontrol #(ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
                         .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
                         .PTEAccessBits, .CAMHit, .TLBMiss, .TLBHit, .TLBPageFault, 
                         .SV39Mode, .Translate);
@@ -122,6 +120,6 @@ module tlb #(parameter TLB_ENTRIES = 8,
   // Replace segments of the virtual page number with segments of the physical
   // page number. For 4 KB pages, the entire virtual page number is replaced.
   // For superpages, some segments are considered offsets into a larger page.
-  tlbmixer Mixer(.VPN, .PPN, .HitPageType, .Address(Address[11:0]), .TLBHit, .TLBPAdr);
+  tlbmixer Mixer(.VPN, .PPN, .HitPageType, .Offset(VAdr[11:0]), .TLBHit, .TLBPAdr);
 
 endmodule

wally-pipelined/src/mmu/tlbcamline.sv

@@ -101,6 +101,6 @@ module tlbcamline #(parameter KEY_BITS = 20,
   // On a flush, zero the valid bit and leave the key unchanged.
   // *** Might we want to update stored key right away to output match on the
   // write cycle? (using a mux)
-  flopenrc #(1) validbitflop(clk, reset, TLBFlush, WriteEnable, 1'b1, Valid);
+  flopenr #(1) validbitflop(clk, reset, WriteEnable | TLBFlush, ~TLBFlush, Valid);
   flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {SATP_ASID, VPN}, Key);
 endmodule

wally-pipelined/src/mmu/tlbcontrol.sv

@@ -25,13 +25,11 @@
 
 `include "wally-config.vh"
 
-// The TLB will have 2**ENTRY_BITS total entries
+module tlbcontrol #(parameter ITLB = 0) (
-module tlbcontrol #(parameter TLB_ENTRIES = 8,
-                    parameter ITLB = 0) (
 
   // Current value of satp CSR (from privileged unit)
   input logic  [`SVMODE_BITS-1:0] SATP_MODE,
-  input logic  [`XLEN-1:0] Address,
+  input logic  [`XLEN-1:0] VAdr,
   input logic              STATUS_MXR, STATUS_SUM, STATUS_MPRV,
   input logic  [1:0]       STATUS_MPP,
   input logic  [1:0]       PrivilegeModeW, // Current privilege level of the processeor
@@ -70,8 +68,8 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
           assign SV39Mode = (SATP_MODE == `SV39);
           // generate page fault if upper bits aren't all the same
           logic UpperEqual39, UpperEqual48;
-          assign UpperEqual39 = &(Address[63:38]) | ~|(Address[63:38]);
+          assign UpperEqual39 = &(VAdr[63:38]) | ~|(VAdr[63:38]);
-          assign UpperEqual48 = &(Address[63:47]) | ~|(Address[63:47]); 
+          assign UpperEqual48 = &(VAdr[63:47]) | ~|(VAdr[63:47]); 
           assign UpperBitsUnequalPageFault = SV39Mode ? ~UpperEqual39 : ~UpperEqual48;
       end else begin
           assign SV39Mode = 0;
@@ -80,7 +78,7 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
   endgenerate
 
   // Determine whether TLB is being used
-  assign TLBAccess = ReadAccess || WriteAccess;
+  assign TLBAccess = ReadAccess | WriteAccess;
 
   // Check whether upper bits of virtual addresss are all equal
 
@@ -122,5 +120,5 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
   endgenerate
 
   assign TLBHit = CAMHit & TLBAccess;
-  assign TLBMiss = ~CAMHit & ~TLBFlush & Translate & TLBAccess;
+  assign TLBMiss = (~CAMHit | TLBFlush) & Translate & TLBAccess;
 endmodule

wally-pipelined/src/mmu/tlbmixer.sv

@@ -32,7 +32,7 @@ module tlbmixer (
     input  logic [`VPN_BITS-1:0]   VPN,
     input  logic [`PPN_BITS-1:0]   PPN,
     input  logic [1:0]             HitPageType,
-    input  logic [11:0]            Address,
+    input  logic [11:0]            Offset,
     input  logic                   TLBHit,
     output logic [`PA_BITS-1:0]    TLBPAdr
 );
@@ -63,6 +63,6 @@ module tlbmixer (
   //assign PPNMixed = (ZeroExtendedVPN & ~PageNumberMask) | (PPN & PageNumberMask);
   // Output the hit physical address if translation is currently on.
   // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal
-  mux2 #(`PA_BITS) hitmux('0, {PPNMixed, Address[11:0]}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system
+  mux2 #(`PA_BITS) hitmux('0, {PPNMixed, Offset}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system
 
 endmodule

wally-pipelined/src/privileged/privileged.sv

@@ -102,6 +102,7 @@ module privileged (
   logic       STATUS_MIE, STATUS_SIE;
   logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW;
   logic md, sd;
+  logic       StallMQ;
 
 
   ///////////////////////////////////////////
@@ -157,8 +158,16 @@ module privileged (
 
   assign BreakpointFaultM = ebreakM; // could have other causes too
   assign EcallFaultM = ecallM;
-  assign ITLBFlushF = sfencevmaM;
+
+  flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
+  assign ITLBFlushF = sfencevmaM & ~StallMQ;
   assign DTLBFlushM = sfencevmaM;
+  // sets ITLBFlush to pulse for one cycle of the sfence.vma instruction
+  // In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program.
+  // But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and 
+  // the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush 
+  // after a cycle AND pulse it for another cycle on any further back-to-back sfences. 
+
 
   // A page fault might occur because of insufficient privilege during a TLB
   // lookup or a improperly formatted page table during walking

wally-pipelined/testbench/testbench-imperas.sv

@@ -61,7 +61,7 @@ string tests32f[] = '{
     "rv32f/I-FCVT-S-WU-01", "2000",
     "rv32f/I-FCVT-W-S-01", "2000",
     "rv32f/I-FCVT-WU-S-01", "2000",
-    // "rv32f/I-FDIV-S-01", "2000",
+    "rv32f/I-FDIV-S-01", "2000",
     "rv32f/I-FEQ-S-01", "2000",
     "rv32f/I-FLE-S-01", "2000",
     "rv32f/I-FLT-S-01", "2000",
@@ -77,7 +77,7 @@ string tests32f[] = '{
     "rv32f/I-FSGNJ-S-01", "2000",
     "rv32f/I-FSGNJN-S-01", "2000",
     "rv32f/I-FSGNJX-S-01", "2000",
-    // "rv32f/I-FSQRT-S-01", "2000",
+    "rv32f/I-FSQRT-S-01", "2000",
     "rv32f/I-FSW-01", "2000",
     "rv32f/I-FLW-01", "2110",
     "rv32f/I-FSUB-S-01", "2000"
@@ -98,7 +98,7 @@ string tests32f[] = '{
     "rv64f/I-FCVT-LU-S-01", "2000",
     "rv64f/I-FCVT-W-S-01", "2000",
     "rv64f/I-FCVT-WU-S-01", "2000",
-    // "rv64f/I-FDIV-S-01", "2000",
+    "rv64f/I-FDIV-S-01", "2000",
     "rv64f/I-FEQ-S-01", "2000",
     "rv64f/I-FLE-S-01", "2000",
     "rv64f/I-FLT-S-01", "2000",
@@ -112,7 +112,7 @@ string tests32f[] = '{
     "rv64f/I-FSGNJ-S-01", "2000",
     "rv64f/I-FSGNJN-S-01", "2000",
     "rv64f/I-FSGNJX-S-01", "2000",
-    // "rv64f/I-FSQRT-S-01", "2000",
+    "rv64f/I-FSQRT-S-01", "2000",
     "rv64f/I-FSUB-S-01", "2000"
   };
 
@@ -121,7 +121,7 @@ string tests32f[] = '{
     "rv64d/I-FLD-01", "2420",
     "rv64d/I-FMV-X-D-01", "2000",
     "rv64d/I-FMV-D-X-01", "2000",
-    // "rv64d/I-FDIV-D-01", "2000",
+    "rv64d/I-FDIV-D-01", "2000",
     "rv64d/I-FCVT-D-L-01", "2000",
     "rv64d/I-FCVT-D-LU-01", "2000",
     "rv64d/I-FCVT-D-S-01", "2000", 
@@ -147,7 +147,7 @@ string tests32f[] = '{
     "rv64d/I-FSGNJ-D-01", "2000",
     "rv64d/I-FSGNJN-D-01", "2000",
     "rv64d/I-FSGNJX-D-01", "2000",
-    // "rv64d/I-FSQRT-D-01", "2000",
+    "rv64d/I-FSQRT-D-01", "2000",
     "rv64d/I-FSUB-D-01", "2000"
   };