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Fixed a bunch of odd bugs with the test bench preventing correct measurement of performance counters.

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This commit is contained in:
Ross Thompson 2023-03-03 17:49:44 -06:00
parent 015104f0ed
commit cab6b9dfc8
3 changed files with 41 additions and 22 deletions
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27
sim/wave.do
View File

@ -6,6 +6,17 @@ add wave -noupdate /testbench/reset
add wave -noupdate /testbench/reset_ext add wave -noupdate /testbench/reset_ext
add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/memfilename
add wave -noupdate /testbench/dut/core/SATP_REGW add wave -noupdate /testbench/dut/core/SATP_REGW
add wave -noupdate /testbench/FunctionName/FunctionName/PCD
add wave -noupdate /testbench/FunctionName/FunctionName/PCE
add wave -noupdate /testbench/FunctionName/FunctionName/PCF
add wave -noupdate /testbench/FunctionName/FunctionName/PCM
add wave -noupdate /testbench/FunctionName/FunctionName/PCM_temp
add wave -noupdate /testbench/FunctionName/FunctionName/PCMOld
add wave -noupdate /testbench/dut/core/InstrValidM
add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr
add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex
add wave -noupdate /testbench/FunctionName/FunctionName/FunctionName
add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrMapLineCount
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
@ -55,11 +66,12 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -group {Execution Stage} /testbench/InstrEName
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
@ -622,10 +634,9 @@ add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheAcc
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheMiss add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheMiss
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/InstrValidNotFlushedM add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/InstrValidNotFlushedM
add wave -noupdate /testbench/clk add wave -noupdate /testbench/clk
add wave -noupdate /testbench/HPMCSample/FinalHPMCOUNTERH
add wave -noupdate /testbench/HPMCSample/InitialHPMCOUNTERH add wave -noupdate /testbench/HPMCSample/InitialHPMCOUNTERH
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {717301 ns} 0} {{Cursor 5} {394987 ns} 1} WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {49231900 ns} 0} {{Cursor 5} {394987 ns} 1}
quietly wave cursor active 4 quietly wave cursor active 4
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 194 configure wave -valuecolwidth 194
@ -641,4 +652,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {717254 ns} {717585 ns} WaveRestoreZoom {49231842 ns} {49231960 ns}

30
testbench/common/functionName.sv
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@ -35,22 +35,29 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
string FunctionName; string FunctionName;
logic [`XLEN-1:0] PCF, PCD, PCE, FunctionAddr; logic [`XLEN-1:0] PCF, PCD, PCE, PCM, FunctionAddr, PCM_temp, PCMOld;
logic StallD, StallE, FlushD, FlushE; logic StallD, StallE, StallM, FlushD, FlushE, FlushM;
logic InstrValidM;
integer ProgramAddrIndex, ProgramAddrIndexQ; integer ProgramAddrIndex, ProgramAddrIndexQ;
assign PCF = testbench.dut.core.ifu.PCF; assign PCF = testbench.dut.core.ifu.PCF;
assign StallD = testbench.dut.core.StallD; assign StallD = testbench.dut.core.StallD;
assign StallE = testbench.dut.core.StallE; assign StallE = testbench.dut.core.StallE;
assign StallM = testbench.dut.core.StallM;
assign FlushD = testbench.dut.core.FlushD; assign FlushD = testbench.dut.core.FlushD;
assign FlushE = testbench.dut.core.FlushE; assign FlushE = testbench.dut.core.FlushE;
assign FlushM = testbench.dut.core.FlushM;
assign InstrValidM = testbench.dut.core.InstrValidM;
// copy from ifu // copy from ifu
// when the F and D stages are flushed we need to ensure the PCE is held so that the function name does not // when the F and D stages are flushed we need to ensure the PCE is held so that the function name does not
// erroneously change. // erroneously change.
flopenrc #(`XLEN) PCDReg(clk, reset, 1'b0, ~StallD, FlushE & FlushD ? PCE : PCF, PCD); // also need to hold the old value not an erroneously fetched PC.
flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, FlushE ? PCE : PCD, PCE); flopenr #(`XLEN) PCDReg(clk, reset, ~StallD, FlushD ? PCE : PCF, PCD);
flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, FlushD & FlushE ? PCF : FlushE ? PCE : PCD, PCE);
flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, FlushD & FlushE & FlushM ? PCF : FlushE & FlushM ? PCE : FlushM ? PCM : PCE, PCM_temp);
flopenr #(`XLEN) PCMOldReg(clk, reset, InstrValidM, PCM_temp, PCMOld);
assign PCM = InstrValidM ? PCM_temp : PCMOld;
task automatic bin_search_min; task automatic bin_search_min;
@ -111,7 +118,11 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
// preload // preload
// initial begin // initial begin
always @ (posedge reset) begin always @ (negedge reset) begin
// clear out the old mapping between programs.
foreach(ProgramAddrMapMemory[i]) ProgramAddrMapMemory.delete(i);
foreach(ProgramLabelMapMemory[i]) ProgramLabelMapMemory.delete(i);
$readmemh(ProgramAddrMapFile, ProgramAddrMapMemory); $readmemh(ProgramAddrMapFile, ProgramAddrMapMemory);
// we need to count the number of lines in the file so we can set FunctionRadixLineCount. // we need to count the number of lines in the file so we can set FunctionRadixLineCount.
@ -147,11 +158,14 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
$display("Cannot open file %s for reading.", ProgramLabelMapFile); $display("Cannot open file %s for reading.", ProgramLabelMapFile);
end end
$fclose(ProgramLabelMapFP); $fclose(ProgramLabelMapFP);
foreach(ProgramAddrMapMemory[i]) $display("%x", ProgramAddrMapMemory[i]);
foreach(ProgramLabelMapMemory[i]) $display("%s", ProgramLabelMapMemory[i]);
end end
always @(PCE) begin always @(PCM) begin
bin_search_min(PCE, ProgramAddrMapLineCount, ProgramAddrMapMemory, FunctionAddr, ProgramAddrIndex); bin_search_min(PCM, ProgramAddrMapLineCount, ProgramAddrMapMemory, FunctionAddr, ProgramAddrIndex);
end end
logic OrReducedAdr, AnyUnknown; logic OrReducedAdr, AnyUnknown;

6
testbench/testbench.sv
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@ -408,7 +408,6 @@ logic [3:0] dummy;
logic StartSample; logic StartSample;
logic EndSample, EndSampleFirst, EndSampleDelayed; logic EndSample, EndSampleFirst, EndSampleDelayed;
logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0]; logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0];
logic [`XLEN-1:0] FinalHPMCOUNTERH[`COUNTERS-1:0];
string HPMCnames[] = '{"Mcycle", string HPMCnames[] = '{"Mcycle",
"------", "------",
@ -464,11 +463,6 @@ logic [3:0] dummy;
InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex]; InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
end end
end end
if(EndSample) begin
for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
FinalHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
end
end
if(EndSample) begin if(EndSample) begin
for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
// unlikely to have more than 10M in any counter. // unlikely to have more than 10M in any counter.