forked from Github_Repos/cvw
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
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Kip Macsai-Goren
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286b4b5b26
commit
c8f80967a6
@ -76,7 +76,7 @@ module ifu (
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// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
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input logic [31:0] HADDR,
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input logic [2:0] HSIZE, HBURST,
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input logic [2:0] HSIZE,
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input logic HWRITE,
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input logic ExecuteAccessF, //read, write, and atomic access are all set to zero because this mmu is onlt working with instructinos in the F stage.
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input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so they're gonna have to come over into ifu and dmem
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@ -42,9 +42,6 @@ module lsu (
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output logic SquashSCW,
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output logic DataMisalignedM,
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// part of the page table walker
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input logic DisableTranslation,
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// address and write data
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input logic [`XLEN-1:0] MemAdrM,
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input logic [`XLEN-1:0] WriteDataM,
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@ -78,6 +75,7 @@ module lsu (
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input logic STATUS_MXR, STATUS_SUM, // from csr
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input logic DTLBWriteM,
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output logic DTLBMissM,
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input logic DisableTranslation, // used to stop intermediate PTE physical addresses being saved to TLB.
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@ -85,7 +83,7 @@ module lsu (
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// PMA/PMP (inside mmu) signals
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input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well.
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input logic [2:0] HSIZE, HBURST,
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input logic [2:0] HSIZE,
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input logic HWRITE,
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input logic AtomicAccessM, WriteAccessM, ReadAccessM, // execute access is hardwired to zero in this mmu because we're only working with data in the M stage.
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input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
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@ -26,29 +26,76 @@
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`include "wally-config.vh"
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module lsuArb
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(input logic clk, reset,
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module lsuArb (
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input logic clk, reset,
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// signals from page table walker
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output logic [`XLEN-1:0] MMUReadPTE,
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input logic MMUTranslate, // *** rename to HPTWReq
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output logic MMUReady,
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input logic [`XLEN-1:0] MMUPAdr,
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// output logic [`XLEN-1:0] MMUReadPTE, // *** it seems like this is the value out of the ahblite that gets sent back to the ptw. I don;t think it needs to get checked until the next paddr has been extracted from it.
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input logic MMUTranslate, // *** rename to HPTWReq
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// output logic MMUReady, // *** Similar reason to mmuReadPTE
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input logic [`XLEN-1:0] MMUPAdr,
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// signal from CPU
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input logic [1:0] MemRWM,
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input logic [2:0] Funct3M,
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input logic [1:0] AtomicM,
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// back to CPU
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output logic CommittedM,
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output logic SquashSCW,
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output logic DataMisalignedM,
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// signal from CPU
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input logic [1:0] MemRWM,
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input logic [2:0] Funct3M,
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input logic [1:0] AtomicM,
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input logic [`XLEN-1:0] MemAdrM, // memory addrress to be checked coming from the CPU. *** this will be used to arbitrate to decide HADDR going into the PM checks, but it also gets sent in its normal form to the lsu because we need the virtual address for the tlb.
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// back to CPU
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// to LSU
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output logic DisableTranslation,
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output logic [1:0] MemRWMtoLSU,
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output logic [2:0] Funct3MtoLSU,
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output logic [1:0] AtomicMtoLSU,
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/* *** unused for not (23 June 2021)
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output logic CommittedM,
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output logic SquashSCW,
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output logic DataMisalignedM,
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*/
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// to LSU
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output logic DisableTranslation,
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output logic [1:0] MemRWMtoLSU,
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output logic [2:0] Funct3MtoLSU,
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output logic [1:0] AtomicMtoLSU
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/* *********** KMG: A lot of the rest of the signals that need to be arbitrated are going to be very annoying
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these are the ones that used to get sent from the ahb to the pma checkers. but our eventual
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goal is to have many of them sent thru the pmp/pma FIRST before the bus can get to them.
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deciding how to choose the right Haddr for the PM checkers will be difficult since they currently get
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HADDR from the ahblite which seems like it could come from any number of sources, while we will eventually be narrowing it down to two possible sources.
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other problems arise when some signals like HSIZE are used in the PM checks but there's also a differnent size input to the tlb and both of these get to go through the mmu.
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which one should be chosen for which device? can the be merged somehow?
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*/
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/*// pmp/pma specifics sent through lsu
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output logic [`XLEN-1:0] HADDRtoLSU,
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output logic [2:0] HSIZEtoLSU // *** May not actually need to be arbitrated, since I'm
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*/
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);
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/* *** these are all the signals that get sent to the pmp/pma chackers straight from the ahblite. We want to switch it around so the
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checkers get these signals first and then the newly checked values can get sent to the ahblite.
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input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well.
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input logic [2:0] HSIZE,
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input logic HWRITE,
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input logic AtomicAccessM, WriteAccessM, ReadAccessM, // execute access is hardwired to zero in this mmu because we're only working with data in the M stage.
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*/
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generate
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if (`XLEN == 32) begin
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assign Funct3MtoLSU = MMUTranslate ? 3'b010 : Funct3M; // *** is this the right thing for the msB?
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end else begin
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assign Funct3MtoLSU = MMUTranslate ? 3'b011 : Funct3M; // *** is this the right thing for the msB?
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end
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endgenerate
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assign AtomicMtoLSU = MMUTranslate ? 2'b00 : AtomicM;
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assign MemRWMtoLSU = MemRWM; // *** along with the rest of the lsu, the mmu uses memrwm in it's pure form so I think we can just forward it through
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assign DisableTranslation = MMUTranslate;
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// assign HADDRtoLSU = MMUTranslate ? MMUPAdr : MemAdrM; // *** Potentially a huge breaking point since the PM checks always get HADDR from ahblite and not necessarily just these two sources. this will need to be looked over when we fix PM to only take physical addresses.
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// assign HSIZEtoLSU = {1'b0, Funct3MtoLSU[1:0]}; // the Hsize is always just the funct3M indicating the size of the data transfer.
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@ -68,7 +68,7 @@ module mmu #(parameter ENTRY_BITS = 3,
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// PMA checker signals
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input logic [31:0] HADDR,
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input logic [2:0] HSIZE, HBURST,
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input logic [2:0] HSIZE,
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input logic HWRITE,
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input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
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input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
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@ -52,7 +52,7 @@ module pagetablewalker (
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// *** modify to send to LSU
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// *** modify to send to LSU // *** KMG: These are inputs/results from the ahblite whose addresses should have already been checked, so I don't think they need to be sent through the LSU
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input logic [`XLEN-1:0] MMUReadPTE,
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input logic MMUReady,
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@ -155,7 +155,12 @@ module wallypipelinedhart (
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logic [4:0] InstrClassM;
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logic [`XLEN-1:0] HRDATAW;
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// IEU vs HPTW arbitration signals to send to LSU
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logic DisableTranslation;
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logic [1:0] MemRWMtoLSU;
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logic [2:0] Funct3MtoLSU;
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logic [1:0] AtomicMtoLSU;
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ifu ifu(.InstrInF(InstrRData), .*); // instruction fetch unit: PC, branch prediction, instruction cache
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@ -174,13 +179,19 @@ module wallypipelinedhart (
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.MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]),
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.*); */
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// arbiter between IEU and pagetablewalker
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lsuArb arbiter(.MMUTranslate(MMUTranslate), .MMUPAdr(MMUPAdr), .MemRWM(MemRWM|FMemRWM),
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.Funct3M(Funct3M), .AtomicM(AtomicM), .MemAdrM(MemAdrM),
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// outputs to LSU
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.DisableTranslation(DisableTranslation), .MemRWMtoLSU(MemRWMtoLSU), .Funct3MtoLSU(Funct3MtoLSU),
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.AtomicMtoLSU(AtomicMtoLSU), .*);
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lsu lsu(.MemRWM(MemRWM|FMemRWM), .WriteDataM(WriteDatatmpM),.*,
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.ReadDataW(ReadDataW),
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.DisableTranslation(1'b0) // *** will connect to page table walker arbiter
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); // data cache unit
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lsu lsu(.MemRWM(MemRWMtoLSU), .AtomicM(AtomicMtoLSU), .Funct3M(Funct3MtoLSU),
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.DisableTranslation(DisableTranslation),
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.WriteDataM(WriteDatatmpM),
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.ReadDataW(ReadDataW), .* ); // data cache unit
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ahblite ebu(
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//.InstrReadF(1'b0),
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