Started constrains file for arty a7 fpga.

2023-03-24 20:38:13 -05:00 · 2023-03-24 20:38:13 -05:00 · c8baffba7c
commit c8baffba7c
parent 3fc0c4b34e
1 changed files with 251 additions and 0 deletions
--- a/fpga/constraints/constraints-artyA7.xdc
+++ b/fpga/constraints/constraints-artyA7.xdc
@ -0,0 +1,251 @@
+# The main clocks are all autogenerated by the Xilinx IP
+# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus.
+# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
+# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
+
+create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
+
+##### GPI ####
+set_property PACKAGE_PIN D9 [get_ports {GPI[0]}]
+set_property PACKAGE_PIN C9 [get_ports {GPI[1]}]
+set_property PACKAGE_PIN B9 [get_ports {GPI[2]}]
+set_property PACKAGE_PIN B8 [get_ports {GPI[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {GPI[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {GPI[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {GPI[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {GPI[0]}]
+set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
+set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
+set_max_delay -from [get_ports {GPI[*]}] 10.000
+
+##### GPO ####
+set_property PACKAGE_PIN G6 [get_ports {GPO[0]}]
+set_property PACKAGE_PIN F6 [get_ports {GPO[1]}]
+set_property PACKAGE_PIN E1 [get_ports {GPO[2]}]
+set_property PACKAGE_PIN G3 [get_ports {GPO[4]}]
+set_property PACKAGE_PIN J4 [get_ports {GPO[3]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[4]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}]
+set_max_delay -to [get_ports {GPO[*]}] 10.000
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}]
+
+
+##### UART #####
+# *** IOSTANDARD is probably wrong
+set_property PACKAGE_PIN A9 [get_ports UARTSin]
+set_property PACKAGE_PIN D0 [get_ports UARTSout]
+set_max_delay -from [get_ports UARTSin] 10.000
+set_max_delay -to [get_ports UARTSout] 10.000
+set_property IOSTANDARD LVCMOS33 [get_ports UARTSin]
+set_property IOSTANDARD LVCMOS3 [get_ports UARTSout]
+set_property DRIVE 6 [get_ports UARTSout]
+set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin]
+set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin]
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports UARTSout]
+
+
+##### reset #####
+#************** reset is inverted
+set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -min -add_delay 2.000 [get_ports reset]
+set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -max -add_delay 2.000 [get_ports reset]
+set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_ports reset]
+set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset]
+set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset]
+set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
+set_max_delay -from [get_ports reset] 15.000
+set_false_path -from [get_ports reset]
+set_property PACKAGE_PIN C2 [get_ports {reset}]
+set_property IOSTANDARD LVCMOS33 [get_ports {reset}]
+
+
+
+##### cpu_reset #####
+# ***********
+set_property PACKAGE_PIN AV36 [get_ports {cpu_reset}]
+set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]
+
+
+##### calib #####
+# **********
+set_property PACKAGE_PIN BA37 [get_ports calib]
+set_property IOSTANDARD LVCMOS12 [get_ports calib]
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
+set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000
+
+
+##### ahblite_resetn #####
+# ***************
+set_property PACKAGE_PIN AU37 [get_ports {ahblite_resetn}]
+set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {ahblite_resetn}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {ahblite_resetn}]
+
+
+##### south_rst #####
+# ***********************
+set_property PACKAGE_PIN BE22 [get_ports south_rst]
+set_property IOSTANDARD LVCMOS18 [get_ports south_rst]
+set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports south_rst]
+set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports south_rst]
+
+
+##### SD Card I/O #####
+#***** may have to switch to Pmod JB or JC.
+set_property PACKAGE_PIN D4 [get_ports {SDCDat[3]}]
+set_property PACKAGE_PIN D2 [get_ports {SDCDat[2]}]
+set_property PACKAGE_PIN E2 [get_ports {SDCDat[1]}]
+set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}]
+set_property PACKAGE_PIN F2 [get_ports SDCCLK]
+set_property PACKAGE_PIN D3 [get_ports {SDCCmd}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
+set_property IOSTANDARD LVCMOS33 [get_ports {SDCCmd}]
+set_property PULLUP true [get_ports {SDCDat[3]}]
+set_property PULLUP true [get_ports {SDCDat[2]}]
+set_property PULLUP true [get_ports {SDCDat[1]}]
+set_property PULLUP true [get_ports {SDCDat[0]}]
+set_property PULLUP true [get_ports {SDCCmd}]
+
+
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
+
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
+
+
+set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
+set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
+
+set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
+
+# *********************************
+set_property DCI_CASCADE {64} [get_iobanks 65]
+set_property INTERNAL_VREF 0.9 [get_iobanks 65]
+
+# ddr3
+
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1]
+set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]
+set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]
+set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]
+set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0]
+set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]
+set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n
+set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n
+set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n
+set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n
+set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0]
+
+
+set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]]
+set_properity PACKAGE_PIN L3 [get_ports ddr3_dq[1]]
+set_properity PACKAGE_PIN K3 [get_ports ddr3_dq[2]]
+set_properity PACKAGE_PIN L6 [get_ports ddr3_dq[3]]
+set_properity PACKAGE_PIN M3 [get_ports ddr3_dq[4]]
+set_properity PACKAGE_PIN M1 [get_ports ddr3_dq[5]]
+set_properity PACKAGE_PIN L4 [get_ports ddr3_dq[6]]
+set_properity PACKAGE_PIN M2 [get_ports ddr3_dq[7]]
+set_properity PACKAGE_PIN V4 [get_ports ddr3_dq[8]]
+set_properity PACKAGE_PIN T5 [get_ports ddr3_dq[9]]
+set_properity PACKAGE_PIN U4 [get_ports ddr3_dq[10]]
+set_properity PACKAGE_PIN V5 [get_ports ddr3_dq[11]]
+set_properity PACKAGE_PIN V1 [get_ports ddr3_dq[12]]
+set_properity PACKAGE_PIN T3 [get_ports ddr3_dq[13]]
+set_properity PACKAGE_PIN U3 [get_ports ddr3_dq[14]]
+set_properity PACKAGE_PIN R3 [get_ports ddr3_dq[15]]
+set_properity PACKAGE_PIN L1 [get_ports ddr3_dm[0]]
+set_properity PACKAGE_PIN U1 [get_ports ddr3_dm[1]]
+set_properity PACKAGE_PIN N2 [get_ports ddr3_dqs_p[0]]
+set_properity PACKAGE_PIN N1 [get_ports ddr3_dqs_n[0]]
+set_properity PACKAGE_PIN U2 [get_ports ddr3_dqs_p[1]]
+set_properity PACKAGE_PIN V2 [get_ports ddr3_dqs_n[1]]
+set_properity PACKAGE_PIN T8 [get_ports ddr3_addr[13]]
+set_properity PACKAGE_PIN T6 [get_ports ddr3_addr[12]]
+set_properity PACKAGE_PIN U6 [get_ports ddr3_addr[11]]
+set_properity PACKAGE_PIN R6 [get_ports ddr3_addr[10]]
+set_properity PACKAGE_PIN V7 [get_ports ddr3_addr[9]]
+set_properity PACKAGE_PIN R8 [get_ports ddr3_addr[8]]
+set_properity PACKAGE_PIN U7 [get_ports ddr3_addr[7]]
+set_properity PACKAGE_PIN V6 [get_ports ddr3_addr[6]]
+set_properity PACKAGE_PIN R7 [get_ports ddr3_addr[5]]
+set_properity PACKAGE_PIN N6 [get_ports ddr3_addr[4]]
+set_properity PACKAGE_PIN T1 [get_ports ddr3_addr[3]]
+set_properity PACKAGE_PIN N4 [get_ports ddr3_addr[2]]
+set_properity PACKAGE_PIN M6 [get_ports ddr3_addr[1]]
+set_properity PACKAGE_PIN R2 [get_ports ddr3_addr[0]]
+set_properity PACKAGE_PIN P2 [get_ports ddr3_ba[2]]
+set_properity PACKAGE_PIN P4 [get_ports ddr3_ba[1]]
+set_properity PACKAGE_PIN R1 [get_ports ddr3_ba[0]]
+set_properity PACKAGE_PIN U9 [get_ports ddr3_ck_p[0]]
+set_properity PACKAGE_PIN V9 [get_ports ddr3_ck_n[0]]
+set_properity PACKAGE_PIN P3 [get_ports ddr3_ras_n]
+set_properity PACKAGE_PIN M4 [get_ports ddr3_cas_n]
+set_properity PACKAGE_PIN P5 [get_ports ddr3_we_n]
+set_properity PACKAGE_PIN K6 [get_ports ddr3_reset_n]
+set_properity PACKAGE_PIN N5 [get_ports ddr3_cke[0]]
+set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]]
+set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
+
+
+
+set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
+
+
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
+
+
+
+set_max_delay -from [get_pins {xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C}] -to [get_ports c0_ddr4_reset_n] 50.000
+
+