forked from Github_Repos/cvw
Add machine-mode timer interrupts to mcause tests
This commit is contained in:
Domenico Ottolia
parent
6fc04768f5
commit
c8a81779ca
@ -345,7 +345,7 @@ module testbench();
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};
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string tests64p[] = '{
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"rv64p/WALLY-MCAUSE", "2000",
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"rv64p/WALLY-MCAUSE", "4000",
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"rv64p/WALLY-SCAUSE", "2000",
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"rv64p/WALLY-MEPC", "5000",
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"rv64p/WALLY-SEPC", "4000",
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@ -360,7 +360,7 @@ module testbench();
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};
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string tests32p[] = '{
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"rv32p/WALLY-MCAUSE", "2000",
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"rv32p/WALLY-MCAUSE", "4000",
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"rv32p/WALLY-SCAUSE", "2000",
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"rv32p/WALLY-MEPC", "5000",
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"rv32p/WALLY-SEPC", "4000",
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@ -1,6 +1,6 @@
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#!/usr/bin/python3
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##################################
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# testgen-CAUSE.py
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# testgen-CAUSE.py (new)
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#
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# dottolia@hmc.edu 1 Mar 2021
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#
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@ -9,8 +9,12 @@
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#
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##################################
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# DOCUMENTATION:
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# Most of the comments explaining what everything
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# does can be found in testgen-TVAL.py
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#
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# The most up-to-date comments explaining what everything
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# does and the layout of the privileged tests
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# can be found in testgen-TVAL.py. This and
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# other files do not have as many comments
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#
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###################################
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##################################
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@ -39,6 +43,35 @@ def randRegs():
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def writeVectors(storecmd, returningInstruction):
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global testnum
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if testMode == "m":
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if fromMode == "m":
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expectedCode = 7 if fromMode == "m" else 5
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clintAddr = "0x2004000"
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writeTest(storecmd, f, r, f"""
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li x1, 0x8
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csrrs x0, {fromMode}status, x1
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la x18, {clintAddr}
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lw x11, 0(x18)
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li x1, 0x3fffffffffffffff
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{storecmd} x1, 0(x18)
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li x1, 0x80
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csrrs x0, {fromMode}ie, x1
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{storecmd} x0, 0(x18)
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""", True, expectedCode, f"""
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li x1, 0x80
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csrrc x0, {fromMode}ie, x1
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li x1, 0x8
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csrrc x0, {fromMode}status, x1
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la x18, {clintAddr}
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{storecmd} x0, 0(x18)
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""")
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# Page 6 of unpriviledged spec
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# For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects
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@ -58,27 +91,28 @@ def writeVectors(storecmd, returningInstruction):
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# """)
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# User Timer Interrupt: True, 4
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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# Supervior timer interrupt: True, 5
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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# Machine timer interrupt: True, 7
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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# if fromMode == "m":
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# clintAddr = "0x2004000"
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# writeTest(storecmd, f, r, f"""
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# li x1, 0x8
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# csrrs x0, {fromMode}status, x1
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# # li x1, 0x8
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# # csrrs x0, mstatus, x1
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# la x18, {clintAddr}
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# lw x11, 0(x18)
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# li x1, 1
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# # li x1, 0x80
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# # csrrs x0, mie, x1
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# # la x18, {clintAddr}
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# # lw x11, 0(x18)
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# # lw x12, 4(x18)
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# # li x1, 1
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# # {storecmd} x1, 0(x18)
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# li x1, 0x80
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# csrrs x0, {fromMode}ie, x1
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# nop
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# sub x1, x2, x3
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# sub x2, x3, x4
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# sub x3, x4, x5
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# nop
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# nop
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# nop
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@ -86,37 +120,20 @@ def writeVectors(storecmd, returningInstruction):
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# nop
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# nop
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# nop
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# """, True, 4, f"""
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# li x1, 0x80
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# # csrrc x0, {fromMode}ie, x1
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# li x1, 0x8
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# # csrrc x0, {fromMode}status, x1
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# la x18, {clintAddr}
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# {storecmd} x11, 0(x18)
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# nop
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# nop
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# nop
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# nop
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# nop
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# nop
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# nop
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# nop
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# nop
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# """, True, 7, f"""
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# # la x18, {clintAddr}
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# # {storecmd} x11, 0(x18)
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# """)
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# writeTest(storecmd, f, r, f"""
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# li x10, MASK_XLEN(0x8)
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# csrrs x0, mstatus, x10
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# li x11, MASK_XLEN(0x80)
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# csrrs x0, mie, x11
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# la x18, 0x2004000
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# lw x11, 0(x18)
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# lw x12, 4(x18)
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# {storecmd} x0, 0(x18)
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# {storecmd} x0, 4(x18)
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# nop
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# nop
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# """, True, 7, "m", f"""
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# la x18, 0x2004000
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# {storecmd} x11, 0(x18)
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# {storecmd} x12, 4(x18)
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# """)
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#writeTest(storecmd, f, r, f"""
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# li x2, 0x0
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#
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@ -157,17 +174,10 @@ def writeVectors(storecmd, returningInstruction):
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# """)
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# User external input: True, 8
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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# Supervisor external input: True, 9
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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# Machine externa input: True, 11
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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# Instruction address misaligned: False, 0
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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# looks like this is giving us an infinite loop for wally
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# BUG: jumping to a misaligned instruction address doesn't cause an exception: we actually jump...
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# Either that, or somehow at the end we always end up at 0x80004002
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@ -178,7 +188,6 @@ def writeVectors(storecmd, returningInstruction):
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# """, False, 0)
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# Instruction access fault: False, 1
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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# Illegal Instruction
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writeTest(storecmd, f, r, f"""
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@ -197,81 +206,82 @@ def writeVectors(storecmd, returningInstruction):
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""", False, 4)
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# Load Access fault: False, 5
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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# Store/AMO address misaligned
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writeTest(storecmd, f, r, f"""
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sw x0, 11(x0)
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""", False, 6)
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# Environment call
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# Environment call from u-mode: only for when only M and U mode enabled?
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# writeTest(storecmd, f, r, f"""
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# ecall
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# """, False, 8, "u")
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if returningInstruction != "ecall":
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if fromMode == "u":
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 8, "u")
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""", False, 8)
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# Environment call from s-mode
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if fromMode == "s":
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 9, "s")
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""", False, 9)
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# Environment call from m-mode
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if fromMode == "m":
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writeTest(storecmd, f, r, f"""
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ecall
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""", False, 11, "m")
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""", False, 11)
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# Instruction page fault: 12
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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# Load page fault: 13
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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# Store/AMO page fault: 15
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# TODO: THIS NEEDS TO BE IMPLEMENTED
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def writeTest(storecmd, f, r, test, interrupt, code, mode = "m", resetHander = ""):
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global testnum
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global testMode
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def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
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global testnum, storeAddressOffset
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expected = code
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if(interrupt):
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expected+=(1 << (xlen - 1))
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trapEnd = ""
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before = ""
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if mode != "m":
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before = f"""
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li x1, 0b110000000000
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csrrc x28, {testMode}status, x1
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li x1, 0b{"01" if mode == "s" else "00"}00000000000
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csrrs x28, {testMode}status, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the mret instruction
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csrrw x27, {testMode}epc, x1
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{testMode}ret
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# From {testMode}, we're now in {mode} mode...
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"""
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trapEnd = f"""j _jend{testnum}"""
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# The code we actually change for our test
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lines = f"""
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li x25, 0xDEADBEA7
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{test}
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_jend{testnum}:
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csrr x25, {testMode}cause
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"""
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# Boilerplate
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#
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# x28 is the address that our trap handler will jump to before returning.
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# This is where we can do our actual tests. After we're done computing and storing
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# what we want, we jump to x27, which continues with the trap handling code (look at the _j_x_trap_... labels)
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#
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lines = f"""
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la x28, _jtest{testnum}
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j _jdo{testnum}
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_jtest{testnum}:
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{lines}
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{resetHander}
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jr x27
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_jdo{testnum}:
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li x25, 0xDEADBEA7
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li gp, 0
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{test}
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"""
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# We expect x25 to be 0 always. This is because of the code we wrote at the begining
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# of this function
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# Store the expected value of x25 to memory and in the .reference_output file
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lines += f"""
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{storecmd} x25, {testnum * wordsize}(x6)
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"""
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lines += storecmd + " x25, " + str(wordsize*testnum) + "(x6)\n"
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f.write(lines)
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if (xlen == 32):
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line = formatrefstr.format(expected)+"\n"
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@ -284,13 +294,13 @@ def writeTest(storecmd, f, r, test, interrupt, code, mode = "m", resetHander = "
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# main body
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##################################
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# change these to suite your tests
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author = "dottolia@hmc.edu"
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xlens = [32, 64]
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numrand = 4;
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testCount = 16;
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# setup
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seed(0xC365DDEB9173AB42) # make tests reproducible
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# Change this seed to a different constant value for every test
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seed(0xC363DAEB9193AB45) # make tests reproducible
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# generate files for each test
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for xlen in xlens:
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@ -304,13 +314,14 @@ for xlen in xlens:
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storecmd = "sd"
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wordsize = 8
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# testMode can be m, s, and u. User mode traps are deprecated, so this should likely just be ["m", "s"]
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for testMode in ["m", "s"]:
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imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
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basename = "WALLY-" + testMode.upper() + "CAUSE"
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fname = imperaspath + "src/" + basename + ".S"
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refname = imperaspath + "references/" + basename + ".reference_output"
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testnum = 0
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storeAddressOffset = 0
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# print custom header part
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f = open(fname, "w")
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@ -337,19 +348,38 @@ for xlen in xlens:
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# two different returning instructions.
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#
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# Current code is written to only support ebreak and ecall.
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for returningInstruction in ["ebreak", "ecall"]:
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#
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# For testgen-TVAL, we don't need to test ebreak, so we can use that as the sole
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# returning instruction. For others, like testgen-CAUSE, we'll need to put
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# both ebreak and ecall here.
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for returningInstruction in ["ebreak"]:
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# All registers used:
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# x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
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# ...
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# x26: expected epc value
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# x28: address trap handler should jump to for the test
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# x27: address the test should return to after the test
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# ...
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# x25: value to write to memory
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# ...
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# x20: intermediate value in trap handler. Don't overwrite this!
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# x19: mtvec old value
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# x18: medeleg old value
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# x17: sedeleg old value
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# x17: sedeleg old value (currently unused — user mode traps deprecated)
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# x16: mideleg old value
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# ...
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# x10 - x14 can be freely written
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# ...
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# x7: copy of x6. Increment this instead of using an offset on x6.
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# this allows us to create more than 2048/wordlen tests.
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# This is the address we write results to
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# x6: Starting address we should write expected results to
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# ...
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# x1 - x5 can be freely written
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# Set up x7 and store old value of mtvec
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lines = f"""
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add x7, x6, x0
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csrr x19, mtvec
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@ -363,90 +393,89 @@ for xlen in xlens:
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csrs sedeleg, x9
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"""
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clintAddr = "0x2004000"
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# Code that will jump to the test (x28 is set in writeTest above)
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testJumpCode = f"""
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auipc x27, 0
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addi x27, x27, 12
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jr x28
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"""
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# Code for handling traps in different modes
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# Some comments are inside of the below strings (prefixed with a #, as you might expected)
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lines += f"""
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# Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode
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li x30, 0
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# Set up
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la x1, _j_m_trap_{returningInstruction}
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csrw mtvec, x1
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la x1, _j_s_trap_{returningInstruction}
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csrw stvec, x1
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la x1, _j_u_trap_{returningInstruction}
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csrw utvec, x1
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# csrw utvec, x1 # user mode traps are not supported
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# Start the tests!
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j _j_t_begin_{returningInstruction}
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# Machine mode traps
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_j_m_trap_{returningInstruction}:
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{testJumpCode if testMode == "m" else "li x25, 0xBAD00003"}
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#li x1, 0x20
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#csrrw x0, mie, x1
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li x11, 0x3fffffffffffffff
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la x18, {clintAddr}
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{storecmd} x11, 0(x18)
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li x1, 0x8
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csrrc x0, mstatus, x1
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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sub x1, x2, x3
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csrrs x1, mepc, x0
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{"csrr x25, mcause" if testMode == "m" else "li x25, 0xBAD00003"}
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addi x1, x1, 4
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csrrw x0, mepc, x1
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csrrs x20, mepc, x0
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addi x20, x20, 4
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csrrw x0, mepc, x20
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bnez x30, _j_all_end_{returningInstruction}
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mret
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# Supervisor mode traps
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_j_s_trap_{returningInstruction}:
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csrrs x1, sepc, x0
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{"csrr x25, scause" if testMode == "s" else "li x25, 0xBAD00001"}
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{testJumpCode if testMode == "s" else "li x25, 0xBAD00001"}
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addi x1, x1, 4
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csrrw x0, sepc, x1
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csrrs x20, sepc, x0
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addi x20, x20, 4
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csrrw x0, sepc, x20
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bnez x30, _j_goto_machine_mode_{returningInstruction}
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sret
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# Unused: user mode traps are no longer supported
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_j_u_trap_{returningInstruction}:
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csrrs x1, uepc, x0
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{"csrr x25, ucause" if testMode == "u" else "li x25, 0xBAD00000"}
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{testJumpCode if testMode == "u" else "li x25, 0xBAD00000"}
|
||||
|
||||
addi x1, x1, 4
|
||||
csrrw x0, uepc, x1
|
||||
csrrs x20, uepc, x0
|
||||
addi x20, x20, 4
|
||||
csrrw x0, uepc, x20
|
||||
bnez x30, _j_goto_supervisor_mode_{returningInstruction}
|
||||
uret
|
||||
|
||||
# Currently unused. Just jumps to _j_goto_machine_mode. If you actually
|
||||
# want to implement this, you'll likely need to reset sedeleg here
|
||||
# and then cause an exception with {returningInstruction} (based on my intuition. Try that first, but I could be missing something / just wrong)
|
||||
_j_goto_supervisor_mode_{returningInstruction}:
|
||||
j _j_goto_machine_mode_{returningInstruction}
|
||||
|
||||
_j_goto_machine_mode_{returningInstruction}:
|
||||
li x30, 1
|
||||
{returningInstruction}
|
||||
li x30, 1 # This will cause us to branch to _j_all_end_{returningInstruction} in the machine trap handler, which we'll get into by invoking...
|
||||
{returningInstruction} # ... this instruction!
|
||||
|
||||
# Run the actual tests!
|
||||
_j_t_begin_{returningInstruction}:
|
||||
"""
|
||||
|
||||
fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
|
||||
|
||||
# We don't want to delegate our returning instruction. Otherwise, we'll have no way of getting
|
||||
# back to machine mode at the end! (and we need to be in machine mode to complete the tests)
|
||||
medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111"
|
||||
|
||||
# Set medeleg and mideleg
|
||||
lines += f"""
|
||||
csrr x18, medeleg
|
||||
li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"}
|
||||
csrw medeleg, x9
|
||||
|
||||
csrr x16, mideleg
|
||||
li x9, {"0xffffffff" if testMode == "s" or testMode == "u" else "0"}
|
||||
csrw mideleg, x9
|
||||
"""
|
||||
|
||||
f.write(lines)
|
||||
@ -454,6 +483,7 @@ for xlen in xlens:
|
||||
for fromMode in fromModeOptions:
|
||||
lines = ""
|
||||
|
||||
# Code to bring us down to supervisor mode
|
||||
if fromMode == "s" or fromMode == "u":
|
||||
lines += f"""
|
||||
li x1, 0b110000000000
|
||||
@ -469,6 +499,7 @@ for xlen in xlens:
|
||||
# We're now in supervisor mode...
|
||||
"""
|
||||
|
||||
# Code to bring us down to user mode
|
||||
if fromMode == "u":
|
||||
lines += f"""
|
||||
|
||||
@ -483,25 +514,33 @@ for xlen in xlens:
|
||||
# We're now in user mode...
|
||||
"""
|
||||
|
||||
# print directed and random test vectors
|
||||
|
||||
f.write(lines)
|
||||
for i in range(0,numrand):
|
||||
for i in range(0,testCount):
|
||||
writeVectors(storecmd, returningInstruction)
|
||||
|
||||
|
||||
# Very end of test. Bring us back up to machine mode
|
||||
# We set x30 to 1, which will cause us to branch to _j_all_end in the
|
||||
# machine mode trap handler, before executing the mret instruction. This will
|
||||
# make us stay in machine mode.
|
||||
#
|
||||
# If we're currently in user mode, this will first bump us up to the supervisor mode
|
||||
# trap handler, which will call returningInstruction again before it's sret instruction,
|
||||
# bumping us up to machine mode
|
||||
#
|
||||
# Get into the trap handler by running returningInstruction (either an ecall or ebreak)
|
||||
f.write(f"""
|
||||
li x30, 1
|
||||
li gp, 0
|
||||
{returningInstruction}
|
||||
_j_all_end_{returningInstruction}:
|
||||
|
||||
# Reset trap handling csrs to old values
|
||||
csrw mtvec, x19
|
||||
csrw medeleg, x18
|
||||
csrw mideleg, x16
|
||||
""")
|
||||
|
||||
# if we're in supervisor mode, this leaves the ebreak instruction untested (we need a way to)
|
||||
# get back to machine mode.
|
||||
|
||||
# print footer
|
||||
h = open("../testgen_footer.S", "r")
|
||||
for line in h:
|
||||
@ -513,6 +552,3 @@ for xlen in xlens:
|
||||
f.write(lines)
|
||||
f.close()
|
||||
r.close()
|
||||
|
||||
|
||||
|
||||
|
||||
@ -52,8 +52,6 @@ def writeVectors(storecmd):
|
||||
# Instruction access fault: False, 1
|
||||
|
||||
# Illegal Instruction
|
||||
#writeTest(storecmd, f, r, "ecall", False, 11)
|
||||
|
||||
writeTest(storecmd, f, r, f"""
|
||||
.fill 1, 4, 0
|
||||
""", False, 2)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user