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make buildroot ignore SSTATUS because QEMU did not originally log it

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This commit is contained in:
bbracker 2021-06-20 05:31:24 -04:00
parent 918ff5093a
commit c77aabdc6f
2 changed files with 40 additions and 3 deletions
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39
wally-pipelined/regression/wave-dos/linux-waves.do
View File

@ -89,7 +89,44 @@ add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[29]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[30] add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[30]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[31] add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[31]
add wave -divider add wave -divider CSRs
add wave -hex sim:/testbench/dut/hart/priv/csr/MSTATUS_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/MCOUNTINHIBIT_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/MCOUNTEREN_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csri/MIDELEG_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csri/MIP_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csri/MIE_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/MTVEC_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTEREN_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/MSCRATCH_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/SSTATUS_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/SCOUNTEREN_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csri/SIP_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csri/SIE_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrs/STVEC_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrs/SCOUNTEREN_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrs/SEDELEG_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrs/SIDELEG_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrs/SATP_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/USTATUS_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UEPC_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UTVEC_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UIP_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrn/UIE_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG01_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG23_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csrm/MISA_REGW
add wave -hex sim:/testbench/dut/hart/priv/csr/genblk1/csru/FRM_REGW
add wave divider
add wave -hex -r /testbench/* add wave -hex -r /testbench/*
# appearance # appearance

4
wally-pipelined/testbench/testbench-linux.sv
View File

@ -396,10 +396,10 @@ module testbench();
string expected``CSR``name; \ string expected``CSR``name; \
//CSR checking \ //CSR checking \
always @(``PATH``.``CSR``_REGW) begin \ always @(``PATH``.``CSR``_REGW) begin \
if ($time > 1) begin \ if ($time > 1 && (`BUILDROOT != 1 || ``CSR``name != SSTATUSstring)) begin \
if (``CSR``name == SEPCstring) begin #1; end \ if (``CSR``name == SEPCstring) begin #1; end \
if (``CSR``name == SCAUSEstring) begin #2; end \ if (``CSR``name == SCAUSEstring) begin #2; end \
if (``CSR``name == SSTATUSstring) begin #4; end \ if (``CSR``name == SSTATUSstring) begin #3; end \
scan_file_csr = $fscanf(data_file_csr, "%s\n", expected``CSR``name); \ scan_file_csr = $fscanf(data_file_csr, "%s\n", expected``CSR``name); \
scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \ scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \
if(expected``CSR``name.icompare(``CSR``name)) begin \ if(expected``CSR``name.icompare(``CSR``name)) begin \