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Added SystemVerilog flag to fma.do so that fma16 compiles properly

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David Harris 2022-03-31 17:00:38 +00:00
parent 54001222cf
commit c7043e4d63
1 changed files with 1 additions and 1 deletions
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pipelined/src/fma/fma.do
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@ -8,7 +8,7 @@ onbreak {resume}
# create library # create library
vlib worklib vlib worklib
vlog -lint -work worklib fma16.v testbench.v vlog -lint -sv -work worklib fma16.v testbench.v
vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt
vsim -lib worklib testbenchopt vsim -lib worklib testbenchopt