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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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bbracker 2022-04-13 05:35:56 -07:00
commit c697c17b05
7 changed files with 44 additions and 38 deletions
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2
fpga/generator/xlnx_ddr4.tcl
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@ -41,7 +41,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
CONFIG.Reference_Clock {Differential} \
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {35} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {30} \
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \

3
pipelined/src/cache/cache.sv vendored
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@ -51,6 +51,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
// lsu control
input logic IgnoreRequestTLB,
input logic IgnoreRequestTrapM,
input logic TrapM,
input logic Cacheable,
// Bus fsm interface
output logic CacheFetchLine,
@ -195,7 +196,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
assign CacheRW = Cacheable ? RW : 2'b00;
assign CacheAtomic = Cacheable ? Atomic : 2'b00;
cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck,
.CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM,
.CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM, .TrapM,
.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdr,
.ClearValid, .ClearDirty, .SetDirty,

3
pipelined/src/cache/cachefsm.sv vendored
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@ -42,6 +42,7 @@ module cachefsm
// interlock fsm
input logic IgnoreRequestTLB,
input logic IgnoreRequestTrapM,
input logic TrapM,
// Bus inputs
input logic CacheBusAck,
// dcache internals
@ -217,7 +218,7 @@ module cachefsm
(CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY;
// **** can this be simplified?
assign SelAdr = (CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss.
assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss.
// use the raw requests as we don't want IgnoreRequestTrapM in the critical path
(CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed
(CurrState == STATE_READY & (CacheRW[1] & CacheHit) & (CPUBusy & `REPLAY)) |

2
pipelined/src/ifu/ifu.sv
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@ -212,7 +212,7 @@ module ifu (
cache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .IgnoreRequestTrapM('0),
icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM(TrapM), .IgnoreRequestTrapM('0),
.CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck),
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
.CacheFetchLine(ICacheFetchLine),

2
pipelined/src/lsu/busfsm.sv
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@ -135,7 +135,7 @@ module busfsm #(parameter integer WordCountThreshold,
(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
(BusCurrState == STATE_BUS_WRITE);
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine);

2
pipelined/src/lsu/lsu.sv
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@ -232,7 +232,7 @@ module lsu (
.ByteMask(ByteMaskM), .WordCount,
.FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM),
.CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
.IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM),
.IgnoreRequestTLB, .IgnoreRequestTrapM, .TrapM(1'b0), .CacheCommitted(DCacheCommittedM),
.CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM),
.CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine),
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));

8
pipelined/src/uncore/uartPC16550D.sv
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@ -143,7 +143,9 @@ module uartPC16550D(
LSR <= #1 8'b01100000;
MSR <= #1 4'b0;
if (`FPGA) begin
DLL <= #1 8'd38;
//DLL <= #1 8'd38; // 35Mhz
//DLL <= #1 8'd11; // 10 Mhz
DLL <= #1 8'd33; // 30 Mhz
DLM <= #1 8'b0;
end else begin
DLL <= #1 8'd1; // this cannot be zero with DLM also zer0.
@ -161,7 +163,9 @@ module uartPC16550D(
-----/\----- EXCLUDED -----/\----- */
// *** BUG FIX ME for now for the divider to be 38. Our clock is 35 Mhz. 35Mhz /(38 * 16) ~= 57600 baud, which is close enough to 57600 baud
// freq /baud / 16 = div
3'b000: if (DLAB) DLL <= #1 8'd38; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
//3'b000: if (DLAB) DLL <= #1 8'd38; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
//3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in
3'b000: if (DLAB) DLL <= #1 8'd33; //else TXHR <= #1 Din; // TX handled in
3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0];
3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing