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merge conflict resolved -- Ross and I made the same fix

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bbracker 2021-05-03 10:10:42 -04:00
commit c643372e1d
2 changed files with 65 additions and 64 deletions
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42
wally-pipelined/src/ifu/localHistoryPredictor.sv
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@ -44,7 +44,7 @@ module localHistoryPredictor
);
logic [2**m-1:0][k-1:0] LHRNextF;
logic [k-1:0] LHRF, LHRFNext, ForwardLHRNext;
logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext;
logic [m-1:0] LookUpPCIndex, UpdatePCIndex;
logic [1:0] PredictionMemory;
logic DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF;
@ -54,19 +54,19 @@ module localHistoryPredictor
assign UpdatePCIndex = {UpdatePC[m+1] ^ UpdatePC[1], UpdatePC[m:2]};
assign LookUpPCIndex = {LookUpPC[m+1] ^ LookUpPC[1], LookUpPC[m:2]};
// INCASE we do ahead pipelining
// SRAM2P1R1W #(m,k) LHR(.clk(clk)),
// .reset(reset),
// .RA1(LookUpPCIndex), // need hashing function to get correct PC address
// .RD1(LHRF),
// .REN1(~StallF),
// .WA1(UpdatePCIndex),
// .WD1(LHRENExt),
// .WEN1(UpdateEN),
// .BitWEN1(2'b11));
// INCASE we do ahead pipelining
// SRAM2P1R1W #(m,k) LHR(.clk(clk)),
// .reset(reset),
// .RA1(LookUpPCIndex), // need hashing function to get correct PC address
// .RD1(LHRF),
// .REN1(~StallF),
// .WA1(UpdatePCIndex),
// .WD1(LHRENExt),
// .WEN1(UpdateEN),
// .BitWEN1(2'b11));
genvar index;
generate
genvar index;
generate
for (index = 0; index < 2**m; index = index +1) begin
flopenr #(k) LocalHistoryRegister(.clk(clk),
@ -75,12 +75,12 @@ generate
.d(LHRFNext),
.q(LHRNextF[index]));
end
endgenerate
endgenerate
// need to forward when updating to the same address as reading.
// first we compare to see if the update and lookup addreses are the same
assign DoForwarding = LookUpPCIndex == UpdatePCIndex;
assign ForwardLHRNext = DoForwarding ? LHRFNext :LHRNextF[LookUpPCIndex];
// need to forward when updating to the same address as reading.
// first we compare to see if the update and lookup addreses are the same
assign DoForwarding = LookUpPCIndex == UpdatePCIndex;
assign ForwardLHRNext = DoForwarding ? LHRFNext :LHRNextF[LookUpPCIndex];
// Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
// LHR referes to the address that the past k branches points to in the prediction stage
@ -97,7 +97,7 @@ assign ForwardLHRNext = DoForwarding ? LHRFNext :LHRNextF[LookUpPCIndex];
assign DoForwardingPHT = LHRFNext == ForwardLHRNext;
assign DoForwardingPHT = LHRFNext == ForwardLHRNext;
// register the update value and the forwarding signal into the Fetch stage
// TODO: add stall logic ***
@ -120,7 +120,7 @@ assign DoForwardingPHT = LHRFNext == ForwardLHRNext;
.clear(FlushF),
.d(ForwardLHRNext),
.q(LHRF));
/*
/*
flopenrc #(k) LHRDReg(.clk(clk),
.reset(reset),
.en(~StallD),
@ -134,5 +134,5 @@ assign DoForwardingPHT = LHRFNext == ForwardLHRNext;
.clear(FlushE),
.d(LHRD),
.q(LHRE));
*/
*/
endmodule

3
wally-pipelined/src/muldiv/div.sv
View File

@ -282,7 +282,8 @@ module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c,
fa fa_inst (a[i], b[i], c[i], sum[i], carry_temp[i+1]);
end
endgenerate
assign carry = {1'b0, carry_temp[WIDTH-1:1], 1'b0};
//assign carry = {1'b0, carry_temp[WIDTH-1:1], 1'b0}; // trmimmed excess bit dh 5/3/21
assign carry = {carry_temp[WIDTH-1:1], 1'b0};
endmodule // adder