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Fixed receive fifo ITNR bug.

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This commit is contained in:
Ross Thompson 2022-05-22 10:55:28 -05:00
parent 92a2ad02db
commit c4f1a0362b
1 changed files with 2 additions and 2 deletions
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4
pipelined/src/uncore/uartPC16550D.sv
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@ -326,8 +326,8 @@ module uartPC16550D(
rxdataready <= #1 1; rxdataready <= #1 1;
end else if (~MEMRb & A == 3'b000 & ~DLAB) begin // reading RBR updates ready / pops fifo end else if (~MEMRb & A == 3'b000 & ~DLAB) begin // reading RBR updates ready / pops fifo
if (fifoenabled) begin if (fifoenabled) begin
if (rxfifotail+1 < rxfifohead) rxfifotail <= #1 rxfifotail + 1; if (~rxfifoempty) rxfifotail <= #1 rxfifotail + 1;
if (rxfifohead == rxfifotail +1) rxdataready <= #1 0; if (rxfifoempty) rxdataready <= #1 0;
end else begin end else begin
rxdataready <= #1 0; rxdataready <= #1 0;
RXBR <= #1 {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode) RXBR <= #1 {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)