Misc typo and indent fixing.

bin/CacheSim.py

@@ -5,7 +5,7 @@
 ##
 ## Written: lserafini@hmc.edu
 ## Created: 27 March 2023
-## Modified: 5 April 2023
+## Modified: 12 April 2023
 ##
 ## Purpose: Simulate a L1 D$ or I$ for comparison with Wally
 ##

sim/rv64gc_CacheSim.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 ###########################################
-## CacheSimTest.py
+## rv64gc_CacheSim.py
 ##
 ## Written: lserafini@hmc.edu
 ## Created: 11 April 2023

src/cache/cachefsm.sv

@@ -55,7 +55,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
   input  logic       FlushAdrFlag,      // On last set of a cache flush
   input  logic       FlushWayFlag,      // On the last way for any set of a cache flush
   output logic       SelAdr,            // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
-  output logic       SetValid,          // Set the dirty bit in the selected way and set
+  output logic       SetValid,          // Set the valid bit in the selected way and set
   output logic       ClearDirty,        // Clear the dirty bit in the selected way and set
   output logic       SetDirty,          // Set the dirty bit in the selected way and set
   output logic       SelWriteback,      // Overrides cached tag check to select a specific way and set for writeback

src/cache/cacheway.sv

@@ -52,7 +52,7 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
   output logic                        HitWay,         // This way hits
   output logic                        ValidWay,       // This way is valid
   output logic                        DirtyWay,       // This way is dirty
-  output logic [TAGLEN-1:0]           TagWay);        // THis way's tag if valid
+  output logic [TAGLEN-1:0]           TagWay);        // This way's tag if valid
 
   localparam                          WORDSPERLINE = LINELEN/`XLEN;
   localparam                          BYTESPERLINE = LINELEN/8;

src/fpu/fsgninj.sv

@@ -48,7 +48,7 @@ module fsgninj (
   
   // format final result based on precision
   //    - uses NaN-blocking format
-  //        - if there are any unsused bits the most significant bits are filled with 1s
+  //        - if there are any unused bits the most significant bits are filled with 1s
   
   if (`FPSIZES == 1)
     assign SgnRes = {ResSgn, X[`FLEN-2:0]};

src/ieu/controller.sv

@@ -300,7 +300,7 @@ module controller(
     assign FlushDCacheD = 0;
   end
  
-  // Decocde stage pipeline control register
+  // Decode stage pipeline control register
   flopenrc #(1)  controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
 
   // Execute stage pipeline control register and logic

src/ieu/datapath.sv

@@ -138,7 +138,8 @@ module datapath (
       assign MulDivResultW = MDUResultW;
     end
   end else begin:fpmux
-    assign IFResultM = IEUResultM; assign IFCvtResultW = IFResultW;
+    assign IFResultM = IEUResultM; 
+    assign IFCvtResultW = IFResultW;
     assign MulDivResultW = MDUResultW;
   end
   mux5  #(`XLEN)  resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); 

src/ifu/decompress.sv

@@ -44,7 +44,7 @@ module decompress (
   logic [5:0]         immSH;
   logic [1:0]         op;
     
-  // Extrac op and register source/destination fields
+  // Extract op and register source/destination fields
   assign instr16 = InstrRawD[15:0]; // instruction is already aligned
   assign op = instr16[1:0];
   assign rds1 = instr16[11:7];

src/ifu/ifu.sv

@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified:
 //
-// Purpose: Instrunction Fetch Unit
+// Purpose: Instruction Fetch Unit
 //           PC, branch prediction, instruction cache
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
@@ -362,7 +362,7 @@ module ifu (
   assign IllegalIEUFPUInstrD = IllegalIEUInstrD & IllegalFPUInstrD;
 
   // Misaligned PC logic
-  // Instruction address misalignement only from br/jal(r) instructions.
+  // Instruction address misalignment only from br/jal(r) instructions.
   // instruction address misalignment is generated by the target of control flow instructions, not
   // the fetch itself.
   // xret and Traps both cannot produce instruction misaligned.
@@ -372,7 +372,7 @@ module ifu (
   // Spec 3.1.14
   // Traps: Can’t happen.  The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4.  See 3.1.7 of the privileged spec.
   assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
-  flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
+  flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
 
   // Instruction and PC/PCLink pipeline registers
   // Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0.

src/privileged/csrsr.sv

@@ -93,7 +93,7 @@ module csrsr (
 
   // harwired STATUS bits
   assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported
-  assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override reigster with 0 if only machine mode supported
+  assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override register with 0 if only machine mode supported
   assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
   assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported
 /*  assign STATUS_UBE = 0; // little-endian