Misc typo and indent fixing.

bin/CacheSim.py

@@ -5,7 +5,7 @@
 ##
 ## Written: lserafini@hmc.edu
 ## Created: 27 March 2023
-## Modified: 5 April 2023
+## Modified: 12 April 2023
 ##
 ## Purpose: Simulate a L1 D$ or I$ for comparison with Wally
 ##

sim/rv64gc_CacheSim.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 
 ###########################################
-## CacheSimTest.py
+## rv64gc_CacheSim.py
 ##
 ## Written: lserafini@hmc.edu
 ## Created: 11 April 2023

src/cache/cachefsm.sv

@@ -47,7 +47,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
   output logic [1:0] CacheBusRW,        // [1] Read (cache line fetch) or [0] write bus (cache line writeback)
   // performance counter outputs
   output logic       CacheMiss,         // Cache miss  
-  output logic       CacheAccess,    // Cache access
+  output logic       CacheAccess,       // Cache access
 
   // cache internals
   input  logic       CacheHit,          // Exactly 1 way hits
@@ -55,7 +55,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
   input  logic       FlushAdrFlag,      // On last set of a cache flush
   input  logic       FlushWayFlag,      // On the last way for any set of a cache flush
   output logic       SelAdr,            // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
-  output logic       SetValid,          // Set the dirty bit in the selected way and set
+  output logic       SetValid,          // Set the valid bit in the selected way and set
   output logic       ClearDirty,        // Clear the dirty bit in the selected way and set
   output logic       SetDirty,          // Set the dirty bit in the selected way and set
   output logic       SelWriteback,      // Overrides cached tag check to select a specific way and set for writeback

src/cache/cacheway.sv

@@ -35,7 +35,7 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
   input  logic                        reset,
   input  logic                        FlushStage,     // Pipeline flush of second stage (prevent writes and bus operations)
   input  logic                        CacheEn,        // Enable the cache memory arrays.  Disable hold read data constant
-  input  logic [$clog2(NUMLINES)-1:0] CacheSet,           // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
+  input  logic [$clog2(NUMLINES)-1:0] CacheSet,       // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
   input  logic [`PA_BITS-1:0]         PAdr,           // Physical address 
   input  logic [LINELEN-1:0]          LineWriteData,  // Final data written to cache (D$ only)
   input  logic                        SetValid,       // Set the valid bit in the selected way and set
@@ -45,14 +45,14 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
   input  logic                        SelFlush,       // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
   input  logic                        VictimWay,      // LRU selected this way as victim to evict
   input  logic                        FlushWay,       // This way is selected for flush and possible writeback if dirty
-  input  logic                        InvalidateCache,//Clear all valid bits
+  input  logic                        InvalidateCache,// Clear all valid bits
   input  logic [LINELEN/8-1:0]        LineByteMask,   // Final byte enables to cache (D$ only)
 
   output logic [LINELEN-1:0]          ReadDataLineWay,// This way's read data if valid
   output logic                        HitWay,         // This way hits
   output logic                        ValidWay,       // This way is valid
   output logic                        DirtyWay,       // This way is dirty
-  output logic [TAGLEN-1:0]           TagWay);        // THis way's tag if valid
+  output logic [TAGLEN-1:0]           TagWay);        // This way's tag if valid
 
   localparam                          WORDSPERLINE = LINELEN/`XLEN;
   localparam                          BYTESPERLINE = LINELEN/8;

src/fpu/fcmp.sv

@@ -71,11 +71,11 @@ module fcmp (
   //    EQ - quiet - sets invalid if signaling NaN input
   always_comb begin
     case (OpCtrl[2:0])
-        3'b110: CmpNV = EitherSNaN;//min 
+        3'b110: CmpNV = EitherSNaN; //min 
-        3'b101: CmpNV = EitherSNaN;//max
+        3'b101: CmpNV = EitherSNaN; //max
-        3'b010: CmpNV = EitherSNaN;//equal
+        3'b010: CmpNV = EitherSNaN; //equal
-        3'b001: CmpNV = EitherNaN;//less than
+        3'b001: CmpNV = EitherNaN;  //less than
-        3'b011: CmpNV = EitherNaN;//less than or equal
+        3'b011: CmpNV = EitherNaN;  //less than or equal
         default: CmpNV = 1'bx;
     endcase
   end 
@@ -137,19 +137,19 @@ module fcmp (
           if(YNaN)    CmpFpRes = NaNRes;   // X = NaN Y = NaN
           else        CmpFpRes = Y;        // X = NaN Y != NaN
         else
-          if(YNaN)    CmpFpRes = X; // X != NaN Y = NaN
+          if(YNaN)    CmpFpRes = X;        // X != NaN Y = NaN
           else // X,Y != NaN
-              if(LT)   CmpFpRes = Y; // X < Y
+              if(LT)  CmpFpRes = Y;        // X < Y
-              else     CmpFpRes = X; // X > Y
+              else    CmpFpRes = X;        // X > Y
     else  // MIN
         if(XNaN)
           if(YNaN)    CmpFpRes = NaNRes;   // X = NaN Y = NaN
           else        CmpFpRes = Y;        // X = NaN Y != NaN
         else
-          if(YNaN)    CmpFpRes = X; // X != NaN Y = NaN
+          if(YNaN)    CmpFpRes = X;        // X != NaN Y = NaN
           else // X,Y != NaN
-              if(LT)   CmpFpRes = X; // X < Y
+              if(LT)  CmpFpRes = X;        // X < Y
-              else     CmpFpRes = Y; // X > Y
+              else    CmpFpRes = Y;        // X > Y
                                   
   // LT/LE/EQ
   //    - -0 = 0

src/fpu/fsgninj.sv

@@ -48,7 +48,7 @@ module fsgninj (
   
   // format final result based on precision
   //    - uses NaN-blocking format
-  //        - if there are any unsused bits the most significant bits are filled with 1s
+  //        - if there are any unused bits the most significant bits are filled with 1s
   
   if (`FPSIZES == 1)
     assign SgnRes = {ResSgn, X[`FLEN-2:0]};

src/ieu/bmu/popcnt.sv

@@ -27,7 +27,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module popcnt #(parameter WIDTH = 32) (
-  input logic  [WIDTH-1:0]            num,    // number to count total ones
+  input logic  [WIDTH-1:0]        num,    // number to count total ones
   output logic [$clog2(WIDTH):0]  PopCnt  // the total number of ones
 );
 

src/ieu/controller.sv

@@ -300,7 +300,7 @@ module controller(
     assign FlushDCacheD = 0;
   end
  
-  // Decocde stage pipeline control register
+  // Decode stage pipeline control register
   flopenrc #(1)  controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
 
   // Execute stage pipeline control register and logic

src/ieu/datapath.sv

@@ -138,7 +138,8 @@ module datapath (
       assign MulDivResultW = MDUResultW;
     end
   end else begin:fpmux
-    assign IFResultM = IEUResultM; assign IFCvtResultW = IFResultW;
+    assign IFResultM = IEUResultM; 
+    assign IFCvtResultW = IFResultW;
     assign MulDivResultW = MDUResultW;
   end
   mux5  #(`XLEN)  resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); 

src/ieu/regfile.sv

@@ -32,7 +32,7 @@
 module regfile (
   input  logic             clk, reset,
   input  logic             we3,                 // Write enable
-  input  logic [ 4:0]      a1, a2, a3,          // Source registers to read (a1, a2), destination register to write (a3)
+  input  logic [4:0]       a1, a2, a3,          // Source registers to read (a1, a2), destination register to write (a3)
   input  logic [`XLEN-1:0] wd3,                 // Write data for port 3
   output logic [`XLEN-1:0] rd1, rd2);           // Read data for ports 1, 2
 

src/ieu/shifter.sv

@@ -32,7 +32,7 @@
 module shifter (
   input  logic [`XLEN-1:0]     A,                             // shift Source
   input  logic [`LOG_XLEN-1:0] Amt,                           // Shift amount
-  input  logic                 Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift
+  input  logic                 Right, Rotate, W64, SubArith,  // Shift right, rotate, W64-type operation, arithmetic shift
   output logic [`XLEN-1:0]     Y);                            // Shifted result
 
   logic [2*`XLEN-2:0]      Z, ZShift;                         // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits

src/ifu/decompress.sv

@@ -44,7 +44,7 @@ module decompress (
   logic [5:0]         immSH;
   logic [1:0]         op;
     
-  // Extrac op and register source/destination fields
+  // Extract op and register source/destination fields
   assign instr16 = InstrRawD[15:0]; // instruction is already aligned
   assign op = instr16[1:0];
   assign rds1 = instr16[11:7];

src/ifu/ifu.sv

@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified:
 //
-// Purpose: Instrunction Fetch Unit
+// Purpose: Instruction Fetch Unit
 //           PC, branch prediction, instruction cache
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
@@ -362,7 +362,7 @@ module ifu (
   assign IllegalIEUFPUInstrD = IllegalIEUInstrD & IllegalFPUInstrD;
 
   // Misaligned PC logic
-  // Instruction address misalignement only from br/jal(r) instructions.
+  // Instruction address misalignment only from br/jal(r) instructions.
   // instruction address misalignment is generated by the target of control flow instructions, not
   // the fetch itself.
   // xret and Traps both cannot produce instruction misaligned.
@@ -372,7 +372,7 @@ module ifu (
   // Spec 3.1.14
   // Traps: Can’t happen.  The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4.  See 3.1.7 of the privileged spec.
   assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
-  flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
+  flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
 
   // Instruction and PC/PCLink pipeline registers
   // Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0.

src/mdu/mdu.sv

@@ -69,8 +69,8 @@ module mdu(
       3'b001: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];    // mulh
       3'b010: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];    // mulhsu
       3'b011: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];    // mulhu
-      3'b100: PrelimResultM = QuotM;                    // div
+      3'b100: PrelimResultM = QuotM;                     // div
-      3'b101: PrelimResultM = QuotM;                    // divu
+      3'b101: PrelimResultM = QuotM;                     // divu
       3'b110: PrelimResultM = RemM;                      // rem
       3'b111: PrelimResultM = RemM;                      // remu
     endcase 

src/mmu/mmu.sv

@@ -49,14 +49,14 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
   output logic                Idempotent,         // PMA indicates memory address is idempotent
   output logic                SelTIM,             // Select a tightly integrated memory
   // Faults
-  output logic                InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM,  // access fault sources
+  output logic                InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources
-  output logic                InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,        // page fault sources
+  output logic                InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,       // page fault sources
-  output logic                UpdateDA,                                                // page fault due to setting dirty or access bit
+  output logic                UpdateDA,                                                  // page fault due to setting dirty or access bit
-  output logic                LoadMisalignedFaultM, StoreAmoMisalignedFaultM,             // misaligned fault sources
+  output logic                LoadMisalignedFaultM, StoreAmoMisalignedFaultM,            // misaligned fault sources
   // PMA checker signals
-  input  logic                 AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,  // access type
+  input  logic                AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,  // access type
-  input var logic [7:0]       PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],                        // PMP configuration
+  input var logic [7:0]       PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],                       // PMP configuration
-  input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]                        // PMP addresses
+  input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]                    // PMP addresses
 );
 
   logic [`PA_BITS-1:0]        TLBPAdr;                  // physical address for TLB                   
@@ -86,7 +86,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
           .DisableTranslation, .PTE, .PageTypeWriteVal,
           .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, 
           .Translate, .TLBPageFault, .UpdateDA);
-  end else begin:tlb// just pass address through as physical
+  end else begin:tlb // just pass address through as physical
     assign Translate = 0;
     assign TLBMiss = 0;
     assign TLBHit = 1; // *** is this necessary

src/privileged/csrsr.sv

@@ -93,7 +93,7 @@ module csrsr (
 
   // harwired STATUS bits
   assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported
-  assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override reigster with 0 if only machine mode supported
+  assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override register with 0 if only machine mode supported
   assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
   assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported
 /*  assign STATUS_UBE = 0; // little-endian