Misc typo and indent fixing.

This commit is contained in:
Limnanthes Serafini 2023-04-13 16:54:15 -07:00
parent ecce9b0ce1
commit c427b4c896
16 changed files with 40 additions and 39 deletions

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@ -5,7 +5,7 @@
## ##
## Written: lserafini@hmc.edu ## Written: lserafini@hmc.edu
## Created: 27 March 2023 ## Created: 27 March 2023
## Modified: 5 April 2023 ## Modified: 12 April 2023
## ##
## Purpose: Simulate a L1 D$ or I$ for comparison with Wally ## Purpose: Simulate a L1 D$ or I$ for comparison with Wally
## ##

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@ -1,7 +1,7 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
########################################### ###########################################
## CacheSimTest.py ## rv64gc_CacheSim.py
## ##
## Written: lserafini@hmc.edu ## Written: lserafini@hmc.edu
## Created: 11 April 2023 ## Created: 11 April 2023

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@ -55,7 +55,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
input logic FlushAdrFlag, // On last set of a cache flush input logic FlushAdrFlag, // On last set of a cache flush
input logic FlushWayFlag, // On the last way for any set of a cache flush input logic FlushWayFlag, // On the last way for any set of a cache flush
output logic SelAdr, // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr output logic SelAdr, // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
output logic SetValid, // Set the dirty bit in the selected way and set output logic SetValid, // Set the valid bit in the selected way and set
output logic ClearDirty, // Clear the dirty bit in the selected way and set output logic ClearDirty, // Clear the dirty bit in the selected way and set
output logic SetDirty, // Set the dirty bit in the selected way and set output logic SetDirty, // Set the dirty bit in the selected way and set
output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback

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@ -45,14 +45,14 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
input logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr input logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
input logic VictimWay, // LRU selected this way as victim to evict input logic VictimWay, // LRU selected this way as victim to evict
input logic FlushWay, // This way is selected for flush and possible writeback if dirty input logic FlushWay, // This way is selected for flush and possible writeback if dirty
input logic InvalidateCache,//Clear all valid bits input logic InvalidateCache,// Clear all valid bits
input logic [LINELEN/8-1:0] LineByteMask, // Final byte enables to cache (D$ only) input logic [LINELEN/8-1:0] LineByteMask, // Final byte enables to cache (D$ only)
output logic [LINELEN-1:0] ReadDataLineWay,// This way's read data if valid output logic [LINELEN-1:0] ReadDataLineWay,// This way's read data if valid
output logic HitWay, // This way hits output logic HitWay, // This way hits
output logic ValidWay, // This way is valid output logic ValidWay, // This way is valid
output logic DirtyWay, // This way is dirty output logic DirtyWay, // This way is dirty
output logic [TAGLEN-1:0] TagWay); // THis way's tag if valid output logic [TAGLEN-1:0] TagWay); // This way's tag if valid
localparam WORDSPERLINE = LINELEN/`XLEN; localparam WORDSPERLINE = LINELEN/`XLEN;
localparam BYTESPERLINE = LINELEN/8; localparam BYTESPERLINE = LINELEN/8;

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@ -71,11 +71,11 @@ module fcmp (
// EQ - quiet - sets invalid if signaling NaN input // EQ - quiet - sets invalid if signaling NaN input
always_comb begin always_comb begin
case (OpCtrl[2:0]) case (OpCtrl[2:0])
3'b110: CmpNV = EitherSNaN;//min 3'b110: CmpNV = EitherSNaN; //min
3'b101: CmpNV = EitherSNaN;//max 3'b101: CmpNV = EitherSNaN; //max
3'b010: CmpNV = EitherSNaN;//equal 3'b010: CmpNV = EitherSNaN; //equal
3'b001: CmpNV = EitherNaN;//less than 3'b001: CmpNV = EitherNaN; //less than
3'b011: CmpNV = EitherNaN;//less than or equal 3'b011: CmpNV = EitherNaN; //less than or equal
default: CmpNV = 1'bx; default: CmpNV = 1'bx;
endcase endcase
end end

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@ -48,7 +48,7 @@ module fsgninj (
// format final result based on precision // format final result based on precision
// - uses NaN-blocking format // - uses NaN-blocking format
// - if there are any unsused bits the most significant bits are filled with 1s // - if there are any unused bits the most significant bits are filled with 1s
if (`FPSIZES == 1) if (`FPSIZES == 1)
assign SgnRes = {ResSgn, X[`FLEN-2:0]}; assign SgnRes = {ResSgn, X[`FLEN-2:0]};

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@ -300,7 +300,7 @@ module controller(
assign FlushDCacheD = 0; assign FlushDCacheD = 0;
end end
// Decocde stage pipeline control register // Decode stage pipeline control register
flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
// Execute stage pipeline control register and logic // Execute stage pipeline control register and logic

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@ -138,7 +138,8 @@ module datapath (
assign MulDivResultW = MDUResultW; assign MulDivResultW = MDUResultW;
end end
end else begin:fpmux end else begin:fpmux
assign IFResultM = IEUResultM; assign IFCvtResultW = IFResultW; assign IFResultM = IEUResultM;
assign IFCvtResultW = IFResultW;
assign MulDivResultW = MDUResultW; assign MulDivResultW = MDUResultW;
end end
mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW);

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@ -32,7 +32,7 @@
module regfile ( module regfile (
input logic clk, reset, input logic clk, reset,
input logic we3, // Write enable input logic we3, // Write enable
input logic [ 4:0] a1, a2, a3, // Source registers to read (a1, a2), destination register to write (a3) input logic [4:0] a1, a2, a3, // Source registers to read (a1, a2), destination register to write (a3)
input logic [`XLEN-1:0] wd3, // Write data for port 3 input logic [`XLEN-1:0] wd3, // Write data for port 3
output logic [`XLEN-1:0] rd1, rd2); // Read data for ports 1, 2 output logic [`XLEN-1:0] rd1, rd2); // Read data for ports 1, 2

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@ -44,7 +44,7 @@ module decompress (
logic [5:0] immSH; logic [5:0] immSH;
logic [1:0] op; logic [1:0] op;
// Extrac op and register source/destination fields // Extract op and register source/destination fields
assign instr16 = InstrRawD[15:0]; // instruction is already aligned assign instr16 = InstrRawD[15:0]; // instruction is already aligned
assign op = instr16[1:0]; assign op = instr16[1:0];
assign rds1 = instr16[11:7]; assign rds1 = instr16[11:7];

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@ -4,7 +4,7 @@
// Written: David_Harris@hmc.edu 9 January 2021 // Written: David_Harris@hmc.edu 9 January 2021
// Modified: // Modified:
// //
// Purpose: Instrunction Fetch Unit // Purpose: Instruction Fetch Unit
// PC, branch prediction, instruction cache // PC, branch prediction, instruction cache
// //
// A component of the CORE-V-WALLY configurable RISC-V project. // A component of the CORE-V-WALLY configurable RISC-V project.
@ -362,7 +362,7 @@ module ifu (
assign IllegalIEUFPUInstrD = IllegalIEUInstrD & IllegalFPUInstrD; assign IllegalIEUFPUInstrD = IllegalIEUInstrD & IllegalFPUInstrD;
// Misaligned PC logic // Misaligned PC logic
// Instruction address misalignement only from br/jal(r) instructions. // Instruction address misalignment only from br/jal(r) instructions.
// instruction address misalignment is generated by the target of control flow instructions, not // instruction address misalignment is generated by the target of control flow instructions, not
// the fetch itself. // the fetch itself.
// xret and Traps both cannot produce instruction misaligned. // xret and Traps both cannot produce instruction misaligned.
@ -372,7 +372,7 @@ module ifu (
// Spec 3.1.14 // Spec 3.1.14
// Traps: Cant happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec. // Traps: Cant happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec.
assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE; assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM); flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
// Instruction and PC/PCLink pipeline registers // Instruction and PC/PCLink pipeline registers
// Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0. // Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0.

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@ -86,7 +86,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
.DisableTranslation, .PTE, .PageTypeWriteVal, .DisableTranslation, .PTE, .PageTypeWriteVal,
.TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit,
.Translate, .TLBPageFault, .UpdateDA); .Translate, .TLBPageFault, .UpdateDA);
end else begin:tlb// just pass address through as physical end else begin:tlb // just pass address through as physical
assign Translate = 0; assign Translate = 0;
assign TLBMiss = 0; assign TLBMiss = 0;
assign TLBHit = 1; // *** is this necessary assign TLBHit = 1; // *** is this necessary

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@ -93,7 +93,7 @@ module csrsr (
// harwired STATUS bits // harwired STATUS bits
assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported
assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override reigster with 0 if only machine mode supported assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override register with 0 if only machine mode supported
assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported
/* assign STATUS_UBE = 0; // little-endian /* assign STATUS_UBE = 0; // little-endian