forked from Github_Repos/cvw
Misc typo and indent fixing.
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@ -5,7 +5,7 @@
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##
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##
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## Written: lserafini@hmc.edu
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## Written: lserafini@hmc.edu
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## Created: 27 March 2023
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## Created: 27 March 2023
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## Modified: 5 April 2023
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## Modified: 12 April 2023
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##
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##
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## Purpose: Simulate a L1 D$ or I$ for comparison with Wally
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## Purpose: Simulate a L1 D$ or I$ for comparison with Wally
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##
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##
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@ -1,7 +1,7 @@
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#!/usr/bin/env python3
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#!/usr/bin/env python3
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###########################################
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###########################################
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## CacheSimTest.py
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## rv64gc_CacheSim.py
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##
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##
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## Written: lserafini@hmc.edu
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## Written: lserafini@hmc.edu
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## Created: 11 April 2023
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## Created: 11 April 2023
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2
src/cache/cachefsm.sv
vendored
2
src/cache/cachefsm.sv
vendored
@ -55,7 +55,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
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input logic FlushAdrFlag, // On last set of a cache flush
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input logic FlushAdrFlag, // On last set of a cache flush
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input logic FlushWayFlag, // On the last way for any set of a cache flush
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input logic FlushWayFlag, // On the last way for any set of a cache flush
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output logic SelAdr, // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
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output logic SelAdr, // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
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output logic SetValid, // Set the dirty bit in the selected way and set
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output logic SetValid, // Set the valid bit in the selected way and set
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output logic ClearDirty, // Clear the dirty bit in the selected way and set
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output logic ClearDirty, // Clear the dirty bit in the selected way and set
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output logic SetDirty, // Set the dirty bit in the selected way and set
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output logic SetDirty, // Set the dirty bit in the selected way and set
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output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback
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output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback
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4
src/cache/cacheway.sv
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4
src/cache/cacheway.sv
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@ -45,14 +45,14 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
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input logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
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input logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
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input logic VictimWay, // LRU selected this way as victim to evict
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input logic VictimWay, // LRU selected this way as victim to evict
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input logic FlushWay, // This way is selected for flush and possible writeback if dirty
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input logic FlushWay, // This way is selected for flush and possible writeback if dirty
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input logic InvalidateCache,//Clear all valid bits
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input logic InvalidateCache,// Clear all valid bits
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input logic [LINELEN/8-1:0] LineByteMask, // Final byte enables to cache (D$ only)
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input logic [LINELEN/8-1:0] LineByteMask, // Final byte enables to cache (D$ only)
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output logic [LINELEN-1:0] ReadDataLineWay,// This way's read data if valid
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output logic [LINELEN-1:0] ReadDataLineWay,// This way's read data if valid
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output logic HitWay, // This way hits
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output logic HitWay, // This way hits
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output logic ValidWay, // This way is valid
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output logic ValidWay, // This way is valid
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output logic DirtyWay, // This way is dirty
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output logic DirtyWay, // This way is dirty
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output logic [TAGLEN-1:0] TagWay); // THis way's tag if valid
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output logic [TAGLEN-1:0] TagWay); // This way's tag if valid
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localparam WORDSPERLINE = LINELEN/`XLEN;
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localparam WORDSPERLINE = LINELEN/`XLEN;
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localparam BYTESPERLINE = LINELEN/8;
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localparam BYTESPERLINE = LINELEN/8;
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@ -71,11 +71,11 @@ module fcmp (
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// EQ - quiet - sets invalid if signaling NaN input
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// EQ - quiet - sets invalid if signaling NaN input
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always_comb begin
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always_comb begin
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case (OpCtrl[2:0])
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case (OpCtrl[2:0])
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3'b110: CmpNV = EitherSNaN;//min
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3'b110: CmpNV = EitherSNaN; //min
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3'b101: CmpNV = EitherSNaN;//max
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3'b101: CmpNV = EitherSNaN; //max
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3'b010: CmpNV = EitherSNaN;//equal
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3'b010: CmpNV = EitherSNaN; //equal
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3'b001: CmpNV = EitherNaN;//less than
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3'b001: CmpNV = EitherNaN; //less than
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3'b011: CmpNV = EitherNaN;//less than or equal
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3'b011: CmpNV = EitherNaN; //less than or equal
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default: CmpNV = 1'bx;
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default: CmpNV = 1'bx;
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endcase
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endcase
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end
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end
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@ -48,7 +48,7 @@ module fsgninj (
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// format final result based on precision
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// format final result based on precision
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// - uses NaN-blocking format
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// - uses NaN-blocking format
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// - if there are any unsused bits the most significant bits are filled with 1s
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// - if there are any unused bits the most significant bits are filled with 1s
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if (`FPSIZES == 1)
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if (`FPSIZES == 1)
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assign SgnRes = {ResSgn, X[`FLEN-2:0]};
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assign SgnRes = {ResSgn, X[`FLEN-2:0]};
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@ -300,7 +300,7 @@ module controller(
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assign FlushDCacheD = 0;
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assign FlushDCacheD = 0;
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end
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end
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// Decocde stage pipeline control register
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// Decode stage pipeline control register
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flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
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flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
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// Execute stage pipeline control register and logic
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// Execute stage pipeline control register and logic
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@ -138,7 +138,8 @@ module datapath (
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assign MulDivResultW = MDUResultW;
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assign MulDivResultW = MDUResultW;
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end
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end
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end else begin:fpmux
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end else begin:fpmux
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assign IFResultM = IEUResultM; assign IFCvtResultW = IFResultW;
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assign IFResultM = IEUResultM;
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assign IFCvtResultW = IFResultW;
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assign MulDivResultW = MDUResultW;
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assign MulDivResultW = MDUResultW;
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end
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end
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mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW);
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mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW);
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@ -32,7 +32,7 @@
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module regfile (
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module regfile (
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input logic clk, reset,
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input logic clk, reset,
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input logic we3, // Write enable
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input logic we3, // Write enable
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input logic [ 4:0] a1, a2, a3, // Source registers to read (a1, a2), destination register to write (a3)
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input logic [4:0] a1, a2, a3, // Source registers to read (a1, a2), destination register to write (a3)
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input logic [`XLEN-1:0] wd3, // Write data for port 3
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input logic [`XLEN-1:0] wd3, // Write data for port 3
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output logic [`XLEN-1:0] rd1, rd2); // Read data for ports 1, 2
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output logic [`XLEN-1:0] rd1, rd2); // Read data for ports 1, 2
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@ -44,7 +44,7 @@ module decompress (
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logic [5:0] immSH;
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logic [5:0] immSH;
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logic [1:0] op;
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logic [1:0] op;
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// Extrac op and register source/destination fields
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// Extract op and register source/destination fields
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assign instr16 = InstrRawD[15:0]; // instruction is already aligned
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assign instr16 = InstrRawD[15:0]; // instruction is already aligned
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assign op = instr16[1:0];
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assign op = instr16[1:0];
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assign rds1 = instr16[11:7];
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assign rds1 = instr16[11:7];
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@ -4,7 +4,7 @@
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// Written: David_Harris@hmc.edu 9 January 2021
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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// Modified:
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//
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//
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// Purpose: Instrunction Fetch Unit
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// Purpose: Instruction Fetch Unit
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// PC, branch prediction, instruction cache
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// PC, branch prediction, instruction cache
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//
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// A component of the CORE-V-WALLY configurable RISC-V project.
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@ -362,7 +362,7 @@ module ifu (
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assign IllegalIEUFPUInstrD = IllegalIEUInstrD & IllegalFPUInstrD;
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assign IllegalIEUFPUInstrD = IllegalIEUInstrD & IllegalFPUInstrD;
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// Misaligned PC logic
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// Misaligned PC logic
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// Instruction address misalignement only from br/jal(r) instructions.
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// Instruction address misalignment only from br/jal(r) instructions.
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// instruction address misalignment is generated by the target of control flow instructions, not
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// instruction address misalignment is generated by the target of control flow instructions, not
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// the fetch itself.
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// the fetch itself.
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// xret and Traps both cannot produce instruction misaligned.
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// xret and Traps both cannot produce instruction misaligned.
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@ -372,7 +372,7 @@ module ifu (
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// Spec 3.1.14
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// Spec 3.1.14
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// Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec.
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// Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec.
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assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
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assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
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flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
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flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
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// Instruction and PC/PCLink pipeline registers
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// Instruction and PC/PCLink pipeline registers
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// Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0.
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// Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0.
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@ -86,7 +86,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
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.DisableTranslation, .PTE, .PageTypeWriteVal,
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.DisableTranslation, .PTE, .PageTypeWriteVal,
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.TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit,
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.TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit,
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.Translate, .TLBPageFault, .UpdateDA);
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.Translate, .TLBPageFault, .UpdateDA);
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end else begin:tlb// just pass address through as physical
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end else begin:tlb // just pass address through as physical
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assign Translate = 0;
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assign Translate = 0;
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assign TLBMiss = 0;
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assign TLBMiss = 0;
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assign TLBHit = 1; // *** is this necessary
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assign TLBHit = 1; // *** is this necessary
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@ -93,7 +93,7 @@ module csrsr (
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// harwired STATUS bits
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// harwired STATUS bits
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assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported
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assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported
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assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override reigster with 0 if only machine mode supported
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assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override register with 0 if only machine mode supported
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assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
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assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
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assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported
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assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported
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/* assign STATUS_UBE = 0; // little-endian
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/* assign STATUS_UBE = 0; // little-endian
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