forked from Github_Repos/cvw
Minor change to btb.
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a9624b1413
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c3e3afe398
@ -50,12 +50,12 @@ module btb #(parameter int Depth = 10 ) (
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logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex;
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logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex;
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logic [`XLEN-1:0] ResetPC;
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logic [`XLEN-1:0] ResetPC;
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logic MatchF, MatchD, MatchE, MatchNextX, MatchXF;
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logic MatchF, MatchD, MatchE, MatchNextX, MatchXF;
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logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF;
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logic [`XLEN+4:0] ForwardBTBPrediction, ForwardBTBPredictionF;
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logic [`XLEN+3:0] TableBTBPredictionF;
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logic [`XLEN+3:0] TableBTBPredictionF;
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logic [`XLEN-1:0] PredPCD;
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logic [`XLEN-1:0] PredPCD;
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logic [3:0] PredInstrClassD; // *** copy of reg outside module
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logic [3:0] PredInstrClassD; // *** copy of reg outside module
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logic UpdateEn;
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logic UpdateEn;
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logic TablePredValidF;
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logic TablePredValidF, PredValidD;
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// hashing function for indexing the PC
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// hashing function for indexing the PC
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// We have Depth bits to index, but XLEN bits as the input.
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// We have Depth bits to index, but XLEN bits as the input.
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@ -72,20 +72,20 @@ module btb #(parameter int Depth = 10 ) (
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assign ResetPC = `RESET_VECTOR;
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assign ResetPC = `RESET_VECTOR;
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assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};
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assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};
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assign MatchF = PCNextFIndex == PCFIndex & PredValidF;
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assign MatchF = PCNextFIndex == PCFIndex;
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assign MatchD = PCNextFIndex == PCDIndex;
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assign MatchD = PCNextFIndex == PCDIndex;
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assign MatchE = PCNextFIndex == PCEIndex;
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assign MatchE = PCNextFIndex == PCEIndex;
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assign MatchNextX = MatchF | MatchD | MatchE;
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assign MatchNextX = MatchF | MatchD | MatchE;
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flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
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flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
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assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} :
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assign ForwardBTBPrediction = MatchF ? {PredValidF, BTBPredInstrClassF, PredPCF} :
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MatchD ? {InstrClassD, PredPCD} :
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MatchD ? {PredValidD, InstrClassD, PredPCD} :
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{InstrClassE, IEUAdrE} ;
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{1'b1, InstrClassE, IEUAdrE} ;
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flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
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flopenr #(`XLEN+5) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
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assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF;
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assign {PredValidF, BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TablePredValidF, TableBTBPredictionF};
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always_ff @ (posedge clk) begin
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always_ff @ (posedge clk) begin
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if (reset) begin
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if (reset) begin
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@ -96,7 +96,7 @@ module btb #(parameter int Depth = 10 ) (
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if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex];
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if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex];
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end
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end
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assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;
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//assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;
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assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE;
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assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE;
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@ -105,6 +105,6 @@ module btb #(parameter int Depth = 10 ) (
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.clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
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.clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
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.ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
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.ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
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flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
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flopenrc #(`XLEN+1) BTBD(clk, reset, FlushD, ~StallD, {PredValidF, PredPCF}, {PredValidD, PredPCD});
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endmodule
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endmodule
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