forked from Github_Repos/cvw
IMMU exclude non word-sized accesses
This commit is contained in:
parent
bfa35d727b
commit
c1786bfec8
@ -201,6 +201,13 @@ coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $l
|
|||||||
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"]
|
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"]
|
||||||
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
|
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
|
||||||
|
|
||||||
|
# IMMU only makes word-sized accesses
|
||||||
|
set line [GetLineNum ../src/mmu/mmu.sv "exclusion-tag: immu-wordaccess"]
|
||||||
|
set line2 [expr $line + 6 ]
|
||||||
|
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item e 1 -fecexprrow 4
|
||||||
|
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item b 1
|
||||||
|
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item s 1
|
||||||
|
|
||||||
# Excluding reset and clear for impossible case in the wficountreg in privdec
|
# Excluding reset and clear for impossible case in the wficountreg in privdec
|
||||||
set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"]
|
set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"]
|
||||||
coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
|
coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
|
||||||
|
@ -128,7 +128,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
|
|||||||
assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~TLBMiss;
|
assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~TLBMiss;
|
||||||
|
|
||||||
// Misaligned faults
|
// Misaligned faults
|
||||||
always_comb
|
always_comb // exclusion-tag: immu-wordaccess
|
||||||
case(Size[1:0])
|
case(Size[1:0])
|
||||||
2'b00: DataMisalignedM = 0; // lb, sb, lbu
|
2'b00: DataMisalignedM = 0; // lb, sb, lbu
|
||||||
2'b01: DataMisalignedM = VAdr[0]; // lh, sh, lhu
|
2'b01: DataMisalignedM = VAdr[0]; // lh, sh, lhu
|
||||||
|
Loading…
Reference in New Issue
Block a user