forked from Github_Repos/cvw
Updated fpga constraints to remove critical warning.
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@ -120,8 +120,6 @@ ebu/ebu.sv: logic HCLK
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ebu/ebu.sv: logic HREADY
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ebu/ebu.sv: logic HRESP
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ebu/ebu.sv: logic HADDR
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ebu/ebu.sv: logic HWDATA
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ebu/ebu.sv: logic HWSTRB
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ebu/ebu.sv: logic HWRITE
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ebu/ebu.sv: logic HSIZE
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ebu/ebu.sv: logic HBURST
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