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Renamed muldiv to mdu

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This commit is contained in:
David Harris 2022-12-27 19:57:10 -08:00
parent dfc0b5d1ad
commit c08811357c
6 changed files with 5 additions and 4 deletions
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1
pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -70,6 +70,7 @@ module fdivsqrtpreproc (
// cout the number of leading zeros // cout the number of leading zeros
// *** W64 muxes conditional on RV64 // *** W64 muxes conditional on RV64
// *** why !FUnct3E
assign AsE = ~Funct3E[0] & (W64E ? ForwardedSrcAE[31] : ForwardedSrcAE[`XLEN-1]); assign AsE = ~Funct3E[0] & (W64E ? ForwardedSrcAE[31] : ForwardedSrcAE[`XLEN-1]);
assign BsE = ~Funct3E[0] & (W64E ? ForwardedSrcBE[31] : ForwardedSrcBE[`XLEN-1]); assign BsE = ~Funct3E[0] & (W64E ? ForwardedSrcBE[31] : ForwardedSrcBE[`XLEN-1]);
assign A64 = W64E ? {{(`XLEN-32){AsE}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE; assign A64 = W64E ? {{(`XLEN-32){AsE}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;

0
pipelined/src/muldiv/intdivrestoring.sv → pipelined/src/mdu/intdivrestoring.sv
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0
pipelined/src/muldiv/intdivrestoringstep.sv → pipelined/src/mdu/intdivrestoringstep.sv
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6
pipelined/src/muldiv/muldiv.sv → pipelined/src/mdu/mdu.sv
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@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// muldiv.sv // mdu.sv
// //
// Written: David_Harris@hmc.edu 9 January 2021 // Written: David_Harris@hmc.edu 9 January 2021
// Modified: // Modified:
@ -30,7 +30,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module muldiv ( module mdu (
input logic clk, reset, input logic clk, reset,
// Execute Stage interface // Execute Stage interface
// input logic [`XLEN-1:0] SrcAE, SrcBE, // input logic [`XLEN-1:0] SrcAE, SrcBE,
@ -94,6 +94,6 @@ module muldiv (
// Writeback stage pipeline register // Writeback stage pipeline register
flopenrc #(`XLEN) MDUResultWReg(clk, reset, FlushW, ~StallW, MDUResultM, MDUResultW); flopenrc #(`XLEN) MDUResultWReg(clk, reset, FlushW, ~StallW, MDUResultM, MDUResultW);
endmodule // muldiv endmodule // mdu

0
pipelined/src/muldiv/mul.sv → pipelined/src/mdu/mul.sv
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2
pipelined/src/wally/wallypipelinedcore.sv
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@ -370,7 +370,7 @@ module wallypipelinedcore (
assign BigEndianM = 0; assign BigEndianM = 0;
end end
if (`M_SUPPORTED) begin:mdu if (`M_SUPPORTED) begin:mdu
muldiv mdu( mdu mdu(
.clk, .reset, .clk, .reset,
.ForwardedSrcAE, .ForwardedSrcBE, .ForwardedSrcAE, .ForwardedSrcBE,
.Funct3E, .Funct3M, .MDUE, .W64E, .Funct3E, .Funct3M, .MDUE, .W64E,