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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
David Harris 2021-12-20 21:09:20 -08:00
commit bf9082b0ad
22 changed files with 680 additions and 1121 deletions
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3
.gitmodules vendored
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[submodule "addins/riscv-arch-test"]
path = addins/riscv-arch-test
url = https://github.com/riscv-non-isa/riscv-arch-test
[submodule "addins/riscv-isa-sim"]
path = addins/riscv-isa-sim
url = https://github.com/riscv-software-src/riscv-isa-sim

1
addins/riscv-isa-sim

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Subproject commit 0f30988e4d0e8daac893834b91979f7700bab481

3
benchmarks/riscv-coremark/multilib.txt Normal file
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If you need to compile for different abi, below is an example of how to configure the gnu riscv toolchain.
./configure --prefix=/import/eager1/ross/riscv-multilib-bin --enable-multilib --multilib-generate="rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv64ic-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--"

317
fpga/constraints/debug.xdc
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##### debugger #####
connect_debug_port u_ila_0/probe34 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]}]]
connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/SDCCmdOE]]
connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/SDCCmdOut]]
connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[64]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[65]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[66]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[67]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[68]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[69]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[70]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[71]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[72]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[73]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[74]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[75]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[76]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[77]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[78]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[79]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[80]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[81]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[82]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[83]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[84]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[85]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[86]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[87]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[88]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[89]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[90]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[91]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[92]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[93]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[94]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_NO_REDO_ANS[95]}]]
connect_debug_port u_ila_0/probe37 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/CountP1[3]}]]
connect_debug_port u_ila_0/probe46 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/instruction_counter/NextCount[3]}]]
connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_RESTARTING]]
connect_debug_port u_ila_0/probe82 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/w_bad_card]]
connect_debug_port u_ila_0/probe83 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_BUSY_EN]]
connect_debug_port u_ila_0/probe89 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/w_resend_last_command]]
connect_debug_port u_ila_0/probe90 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_SD_CMD_RX]]
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list wrapper_i/ddr4_0/inst/u_ddr4_infrastructure/addn_ui_clkout1]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 12 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/hart/priv/trap/PendingIntsM[0]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[1]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[2]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[3]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[4]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[5]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[6]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[7]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[8]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[9]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[10]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[11]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 4 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 4 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 4 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 6 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[11]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 64 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 64 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 64 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 6 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[11]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 64 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 6 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MIP_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[11]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 64 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 6 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MIE_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[11]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 64 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 3 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SIP_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SIP_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SIP_REGW[9]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 63 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 3 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SIE_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SIE_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SIE_REGW[9]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 64 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/hart/ReadDataM[0]} {wallypipelinedsoc/hart/ReadDataM[1]} {wallypipelinedsoc/hart/ReadDataM[2]} {wallypipelinedsoc/hart/ReadDataM[3]} {wallypipelinedsoc/hart/ReadDataM[4]} {wallypipelinedsoc/hart/ReadDataM[5]} {wallypipelinedsoc/hart/ReadDataM[6]} {wallypipelinedsoc/hart/ReadDataM[7]} {wallypipelinedsoc/hart/ReadDataM[8]} {wallypipelinedsoc/hart/ReadDataM[9]} {wallypipelinedsoc/hart/ReadDataM[10]} {wallypipelinedsoc/hart/ReadDataM[11]} {wallypipelinedsoc/hart/ReadDataM[12]} {wallypipelinedsoc/hart/ReadDataM[13]} {wallypipelinedsoc/hart/ReadDataM[14]} {wallypipelinedsoc/hart/ReadDataM[15]} {wallypipelinedsoc/hart/ReadDataM[16]} {wallypipelinedsoc/hart/ReadDataM[17]} {wallypipelinedsoc/hart/ReadDataM[18]} {wallypipelinedsoc/hart/ReadDataM[19]} {wallypipelinedsoc/hart/ReadDataM[20]} {wallypipelinedsoc/hart/ReadDataM[21]} {wallypipelinedsoc/hart/ReadDataM[22]} {wallypipelinedsoc/hart/ReadDataM[23]} {wallypipelinedsoc/hart/ReadDataM[24]} {wallypipelinedsoc/hart/ReadDataM[25]} {wallypipelinedsoc/hart/ReadDataM[26]} {wallypipelinedsoc/hart/ReadDataM[27]} {wallypipelinedsoc/hart/ReadDataM[28]} {wallypipelinedsoc/hart/ReadDataM[29]} {wallypipelinedsoc/hart/ReadDataM[30]} {wallypipelinedsoc/hart/ReadDataM[31]} {wallypipelinedsoc/hart/ReadDataM[32]} {wallypipelinedsoc/hart/ReadDataM[33]} {wallypipelinedsoc/hart/ReadDataM[34]} {wallypipelinedsoc/hart/ReadDataM[35]} {wallypipelinedsoc/hart/ReadDataM[36]} {wallypipelinedsoc/hart/ReadDataM[37]} {wallypipelinedsoc/hart/ReadDataM[38]} {wallypipelinedsoc/hart/ReadDataM[39]} {wallypipelinedsoc/hart/ReadDataM[40]} {wallypipelinedsoc/hart/ReadDataM[41]} {wallypipelinedsoc/hart/ReadDataM[42]} {wallypipelinedsoc/hart/ReadDataM[43]} {wallypipelinedsoc/hart/ReadDataM[44]} {wallypipelinedsoc/hart/ReadDataM[45]} {wallypipelinedsoc/hart/ReadDataM[46]} {wallypipelinedsoc/hart/ReadDataM[47]} {wallypipelinedsoc/hart/ReadDataM[48]} {wallypipelinedsoc/hart/ReadDataM[49]} {wallypipelinedsoc/hart/ReadDataM[50]} {wallypipelinedsoc/hart/ReadDataM[51]} {wallypipelinedsoc/hart/ReadDataM[52]} {wallypipelinedsoc/hart/ReadDataM[53]} {wallypipelinedsoc/hart/ReadDataM[54]} {wallypipelinedsoc/hart/ReadDataM[55]} {wallypipelinedsoc/hart/ReadDataM[56]} {wallypipelinedsoc/hart/ReadDataM[57]} {wallypipelinedsoc/hart/ReadDataM[58]} {wallypipelinedsoc/hart/ReadDataM[59]} {wallypipelinedsoc/hart/ReadDataM[60]} {wallypipelinedsoc/hart/ReadDataM[61]} {wallypipelinedsoc/hart/ReadDataM[62]} {wallypipelinedsoc/hart/ReadDataM[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property port_width 64 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/hart/WriteDataM[0]} {wallypipelinedsoc/hart/WriteDataM[1]} {wallypipelinedsoc/hart/WriteDataM[2]} {wallypipelinedsoc/hart/WriteDataM[3]} {wallypipelinedsoc/hart/WriteDataM[4]} {wallypipelinedsoc/hart/WriteDataM[5]} {wallypipelinedsoc/hart/WriteDataM[6]} {wallypipelinedsoc/hart/WriteDataM[7]} {wallypipelinedsoc/hart/WriteDataM[8]} {wallypipelinedsoc/hart/WriteDataM[9]} {wallypipelinedsoc/hart/WriteDataM[10]} {wallypipelinedsoc/hart/WriteDataM[11]} {wallypipelinedsoc/hart/WriteDataM[12]} {wallypipelinedsoc/hart/WriteDataM[13]} {wallypipelinedsoc/hart/WriteDataM[14]} {wallypipelinedsoc/hart/WriteDataM[15]} {wallypipelinedsoc/hart/WriteDataM[16]} {wallypipelinedsoc/hart/WriteDataM[17]} {wallypipelinedsoc/hart/WriteDataM[18]} {wallypipelinedsoc/hart/WriteDataM[19]} {wallypipelinedsoc/hart/WriteDataM[20]} {wallypipelinedsoc/hart/WriteDataM[21]} {wallypipelinedsoc/hart/WriteDataM[22]} {wallypipelinedsoc/hart/WriteDataM[23]} {wallypipelinedsoc/hart/WriteDataM[24]} {wallypipelinedsoc/hart/WriteDataM[25]} {wallypipelinedsoc/hart/WriteDataM[26]} {wallypipelinedsoc/hart/WriteDataM[27]} {wallypipelinedsoc/hart/WriteDataM[28]} {wallypipelinedsoc/hart/WriteDataM[29]} {wallypipelinedsoc/hart/WriteDataM[30]} {wallypipelinedsoc/hart/WriteDataM[31]} {wallypipelinedsoc/hart/WriteDataM[32]} {wallypipelinedsoc/hart/WriteDataM[33]} {wallypipelinedsoc/hart/WriteDataM[34]} {wallypipelinedsoc/hart/WriteDataM[35]} {wallypipelinedsoc/hart/WriteDataM[36]} {wallypipelinedsoc/hart/WriteDataM[37]} {wallypipelinedsoc/hart/WriteDataM[38]} {wallypipelinedsoc/hart/WriteDataM[39]} {wallypipelinedsoc/hart/WriteDataM[40]} {wallypipelinedsoc/hart/WriteDataM[41]} {wallypipelinedsoc/hart/WriteDataM[42]} {wallypipelinedsoc/hart/WriteDataM[43]} {wallypipelinedsoc/hart/WriteDataM[44]} {wallypipelinedsoc/hart/WriteDataM[45]} {wallypipelinedsoc/hart/WriteDataM[46]} {wallypipelinedsoc/hart/WriteDataM[47]} {wallypipelinedsoc/hart/WriteDataM[48]} {wallypipelinedsoc/hart/WriteDataM[49]} {wallypipelinedsoc/hart/WriteDataM[50]} {wallypipelinedsoc/hart/WriteDataM[51]} {wallypipelinedsoc/hart/WriteDataM[52]} {wallypipelinedsoc/hart/WriteDataM[53]} {wallypipelinedsoc/hart/WriteDataM[54]} {wallypipelinedsoc/hart/WriteDataM[55]} {wallypipelinedsoc/hart/WriteDataM[56]} {wallypipelinedsoc/hart/WriteDataM[57]} {wallypipelinedsoc/hart/WriteDataM[58]} {wallypipelinedsoc/hart/WriteDataM[59]} {wallypipelinedsoc/hart/WriteDataM[60]} {wallypipelinedsoc/hart/WriteDataM[61]} {wallypipelinedsoc/hart/WriteDataM[62]} {wallypipelinedsoc/hart/WriteDataM[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property port_width 3 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[2]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property port_width 5 [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[3]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
set_property port_width 4 [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
set_property port_width 4 [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
set_property port_width 64 [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/HWDATA[0]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[1]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[2]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[3]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[4]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[5]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[6]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[7]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[8]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[9]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[10]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[11]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[12]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[13]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[14]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[15]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[16]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[17]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[18]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[19]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[20]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[21]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[22]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[23]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[24]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[25]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[26]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[27]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[28]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[29]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[30]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[31]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[32]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[33]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[34]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[35]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[36]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[37]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[38]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[39]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[40]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[41]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[42]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[43]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[44]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[45]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[46]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[47]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[48]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[49]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[50]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[51]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[52]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[53]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[54]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[55]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[56]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[57]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[58]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[59]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[60]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[61]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[62]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
set_property port_width 64 [get_debug_ports u_ila_0/probe24]
connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/HRDATA[0]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[1]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[2]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[3]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[4]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[5]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[6]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[7]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[8]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[9]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[10]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[11]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[12]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[13]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[14]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[15]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[16]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[17]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[18]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[19]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[20]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[21]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[22]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[23]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[24]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[25]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[26]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[27]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[28]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[29]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[30]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[31]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[32]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[33]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[34]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[35]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[36]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[37]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[38]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[39]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[40]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[41]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[42]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[43]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[44]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[45]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[46]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[47]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[48]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[49]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[50]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[51]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[52]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[53]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[54]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[55]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[56]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[57]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[58]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[59]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[60]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[61]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[62]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
set_property port_width 32 [get_debug_ports u_ila_0/probe25]
connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[0]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[1]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[2]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[3]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[4]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[5]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[6]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[7]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[8]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[9]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[10]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[11]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[12]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[13]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[14]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[15]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[16]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[17]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[18]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[19]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[20]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[21]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[22]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[23]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[24]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[25]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[26]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[27]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[28]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[29]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[30]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
set_property port_width 2 [get_debug_ports u_ila_0/probe26]
connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[0]} {wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
set_property port_width 32 [get_debug_ports u_ila_0/probe27]
connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[0]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[1]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[2]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[3]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[4]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[5]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[6]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[7]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[8]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[9]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[10]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[11]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[12]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[13]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[14]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[15]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[16]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[17]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[18]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[19]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[20]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[21]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[22]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[23]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[24]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[25]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[26]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[27]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[28]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[29]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[30]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
set_property port_width 64 [get_debug_ports u_ila_0/probe28]
connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/hart/PCM[0]} {wallypipelinedsoc/hart/PCM[1]} {wallypipelinedsoc/hart/PCM[2]} {wallypipelinedsoc/hart/PCM[3]} {wallypipelinedsoc/hart/PCM[4]} {wallypipelinedsoc/hart/PCM[5]} {wallypipelinedsoc/hart/PCM[6]} {wallypipelinedsoc/hart/PCM[7]} {wallypipelinedsoc/hart/PCM[8]} {wallypipelinedsoc/hart/PCM[9]} {wallypipelinedsoc/hart/PCM[10]} {wallypipelinedsoc/hart/PCM[11]} {wallypipelinedsoc/hart/PCM[12]} {wallypipelinedsoc/hart/PCM[13]} {wallypipelinedsoc/hart/PCM[14]} {wallypipelinedsoc/hart/PCM[15]} {wallypipelinedsoc/hart/PCM[16]} {wallypipelinedsoc/hart/PCM[17]} {wallypipelinedsoc/hart/PCM[18]} {wallypipelinedsoc/hart/PCM[19]} {wallypipelinedsoc/hart/PCM[20]} {wallypipelinedsoc/hart/PCM[21]} {wallypipelinedsoc/hart/PCM[22]} {wallypipelinedsoc/hart/PCM[23]} {wallypipelinedsoc/hart/PCM[24]} {wallypipelinedsoc/hart/PCM[25]} {wallypipelinedsoc/hart/PCM[26]} {wallypipelinedsoc/hart/PCM[27]} {wallypipelinedsoc/hart/PCM[28]} {wallypipelinedsoc/hart/PCM[29]} {wallypipelinedsoc/hart/PCM[30]} {wallypipelinedsoc/hart/PCM[31]} {wallypipelinedsoc/hart/PCM[32]} {wallypipelinedsoc/hart/PCM[33]} {wallypipelinedsoc/hart/PCM[34]} {wallypipelinedsoc/hart/PCM[35]} {wallypipelinedsoc/hart/PCM[36]} {wallypipelinedsoc/hart/PCM[37]} {wallypipelinedsoc/hart/PCM[38]} {wallypipelinedsoc/hart/PCM[39]} {wallypipelinedsoc/hart/PCM[40]} {wallypipelinedsoc/hart/PCM[41]} {wallypipelinedsoc/hart/PCM[42]} {wallypipelinedsoc/hart/PCM[43]} {wallypipelinedsoc/hart/PCM[44]} {wallypipelinedsoc/hart/PCM[45]} {wallypipelinedsoc/hart/PCM[46]} {wallypipelinedsoc/hart/PCM[47]} {wallypipelinedsoc/hart/PCM[48]} {wallypipelinedsoc/hart/PCM[49]} {wallypipelinedsoc/hart/PCM[50]} {wallypipelinedsoc/hart/PCM[51]} {wallypipelinedsoc/hart/PCM[52]} {wallypipelinedsoc/hart/PCM[53]} {wallypipelinedsoc/hart/PCM[54]} {wallypipelinedsoc/hart/PCM[55]} {wallypipelinedsoc/hart/PCM[56]} {wallypipelinedsoc/hart/PCM[57]} {wallypipelinedsoc/hart/PCM[58]} {wallypipelinedsoc/hart/PCM[59]} {wallypipelinedsoc/hart/PCM[60]} {wallypipelinedsoc/hart/PCM[61]} {wallypipelinedsoc/hart/PCM[62]} {wallypipelinedsoc/hart/PCM[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
set_property port_width 64 [get_debug_ports u_ila_0/probe29]
connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/hart/MemAdrM[0]} {wallypipelinedsoc/hart/MemAdrM[1]} {wallypipelinedsoc/hart/MemAdrM[2]} {wallypipelinedsoc/hart/MemAdrM[3]} {wallypipelinedsoc/hart/MemAdrM[4]} {wallypipelinedsoc/hart/MemAdrM[5]} {wallypipelinedsoc/hart/MemAdrM[6]} {wallypipelinedsoc/hart/MemAdrM[7]} {wallypipelinedsoc/hart/MemAdrM[8]} {wallypipelinedsoc/hart/MemAdrM[9]} {wallypipelinedsoc/hart/MemAdrM[10]} {wallypipelinedsoc/hart/MemAdrM[11]} {wallypipelinedsoc/hart/MemAdrM[12]} {wallypipelinedsoc/hart/MemAdrM[13]} {wallypipelinedsoc/hart/MemAdrM[14]} {wallypipelinedsoc/hart/MemAdrM[15]} {wallypipelinedsoc/hart/MemAdrM[16]} {wallypipelinedsoc/hart/MemAdrM[17]} {wallypipelinedsoc/hart/MemAdrM[18]} {wallypipelinedsoc/hart/MemAdrM[19]} {wallypipelinedsoc/hart/MemAdrM[20]} {wallypipelinedsoc/hart/MemAdrM[21]} {wallypipelinedsoc/hart/MemAdrM[22]} {wallypipelinedsoc/hart/MemAdrM[23]} {wallypipelinedsoc/hart/MemAdrM[24]} {wallypipelinedsoc/hart/MemAdrM[25]} {wallypipelinedsoc/hart/MemAdrM[26]} {wallypipelinedsoc/hart/MemAdrM[27]} {wallypipelinedsoc/hart/MemAdrM[28]} {wallypipelinedsoc/hart/MemAdrM[29]} {wallypipelinedsoc/hart/MemAdrM[30]} {wallypipelinedsoc/hart/MemAdrM[31]} {wallypipelinedsoc/hart/MemAdrM[32]} {wallypipelinedsoc/hart/MemAdrM[33]} {wallypipelinedsoc/hart/MemAdrM[34]} {wallypipelinedsoc/hart/MemAdrM[35]} {wallypipelinedsoc/hart/MemAdrM[36]} {wallypipelinedsoc/hart/MemAdrM[37]} {wallypipelinedsoc/hart/MemAdrM[38]} {wallypipelinedsoc/hart/MemAdrM[39]} {wallypipelinedsoc/hart/MemAdrM[40]} {wallypipelinedsoc/hart/MemAdrM[41]} {wallypipelinedsoc/hart/MemAdrM[42]} {wallypipelinedsoc/hart/MemAdrM[43]} {wallypipelinedsoc/hart/MemAdrM[44]} {wallypipelinedsoc/hart/MemAdrM[45]} {wallypipelinedsoc/hart/MemAdrM[46]} {wallypipelinedsoc/hart/MemAdrM[47]} {wallypipelinedsoc/hart/MemAdrM[48]} {wallypipelinedsoc/hart/MemAdrM[49]} {wallypipelinedsoc/hart/MemAdrM[50]} {wallypipelinedsoc/hart/MemAdrM[51]} {wallypipelinedsoc/hart/MemAdrM[52]} {wallypipelinedsoc/hart/MemAdrM[53]} {wallypipelinedsoc/hart/MemAdrM[54]} {wallypipelinedsoc/hart/MemAdrM[55]} {wallypipelinedsoc/hart/MemAdrM[56]} {wallypipelinedsoc/hart/MemAdrM[57]} {wallypipelinedsoc/hart/MemAdrM[58]} {wallypipelinedsoc/hart/MemAdrM[59]} {wallypipelinedsoc/hart/MemAdrM[60]} {wallypipelinedsoc/hart/MemAdrM[61]} {wallypipelinedsoc/hart/MemAdrM[62]} {wallypipelinedsoc/hart/MemAdrM[63]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
set_property port_width 2 [get_debug_ports u_ila_0/probe30]
connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/hart/MemRWM[0]} {wallypipelinedsoc/hart/MemRWM[1]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
set_property port_width 32 [get_debug_ports u_ila_0/probe31]
connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/hart/InstrM[0]} {wallypipelinedsoc/hart/InstrM[1]} {wallypipelinedsoc/hart/InstrM[2]} {wallypipelinedsoc/hart/InstrM[3]} {wallypipelinedsoc/hart/InstrM[4]} {wallypipelinedsoc/hart/InstrM[5]} {wallypipelinedsoc/hart/InstrM[6]} {wallypipelinedsoc/hart/InstrM[7]} {wallypipelinedsoc/hart/InstrM[8]} {wallypipelinedsoc/hart/InstrM[9]} {wallypipelinedsoc/hart/InstrM[10]} {wallypipelinedsoc/hart/InstrM[11]} {wallypipelinedsoc/hart/InstrM[12]} {wallypipelinedsoc/hart/InstrM[13]} {wallypipelinedsoc/hart/InstrM[14]} {wallypipelinedsoc/hart/InstrM[15]} {wallypipelinedsoc/hart/InstrM[16]} {wallypipelinedsoc/hart/InstrM[17]} {wallypipelinedsoc/hart/InstrM[18]} {wallypipelinedsoc/hart/InstrM[19]} {wallypipelinedsoc/hart/InstrM[20]} {wallypipelinedsoc/hart/InstrM[21]} {wallypipelinedsoc/hart/InstrM[22]} {wallypipelinedsoc/hart/InstrM[23]} {wallypipelinedsoc/hart/InstrM[24]} {wallypipelinedsoc/hart/InstrM[25]} {wallypipelinedsoc/hart/InstrM[26]} {wallypipelinedsoc/hart/InstrM[27]} {wallypipelinedsoc/hart/InstrM[28]} {wallypipelinedsoc/hart/InstrM[29]} {wallypipelinedsoc/hart/InstrM[30]} {wallypipelinedsoc/hart/InstrM[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBAck]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBRead]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBWrite]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/hart/priv/trap/BreakpointFaultM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/hart/priv/trap/EcallFaultM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DAT0_Q]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DATA_CRC16_GOOD]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_DAT_TIMES_OUT]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/hart/priv/trap/IllegalInstrFaultM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/hart/priv/trap/InstrAccessFaultM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/hart/priv/trap/InstrPageFaultM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/hart/InstrValidM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadAccessFaultM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadMisalignedFaultM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadPageFaultM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/hart/priv/trap/mretM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/o_G_CLK_SD_EN]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CLK]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD_OE]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_CMD_OE]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsoc/hart/priv/trap/sretM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsoc/hart/priv/trap/StoreAccessFaultM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/hart/priv/trap/StoreMisalignedFaultM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/hart/priv/trap/StorePageFaultM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/hart/TrapM]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_EN]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_RST]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_UP_DOWN]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
connect_debug_port u_ila_0/probe63 [get_nets [list wallypipelinedsoc/uncore/uart.uart/DTRb]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/uncore/uart.uart/INTR]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
set_property port_width 1 [get_debug_ports u_ila_0/probe65]
connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/uncore/uart.uart/OUT1b]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
set_property port_width 1 [get_debug_ports u_ila_0/probe66]
connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/uncore/uart.uart/OUT2b]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
set_property port_width 1 [get_debug_ports u_ila_0/probe67]
connect_debug_port u_ila_0/probe67 [get_nets [list wallypipelinedsoc/uncore/uart.uart/RTSb]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
set_property port_width 1 [get_debug_ports u_ila_0/probe68]
connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/uncore/uart.uart/RXRDYb]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
set_property port_width 1 [get_debug_ports u_ila_0/probe69]
connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/uncore/uart.uart/SIN]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
set_property port_width 1 [get_debug_ports u_ila_0/probe70]
connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/uncore/uart.uart/SOUT]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71]
set_property port_width 1 [get_debug_ports u_ila_0/probe71]
connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/uncore/uart.uart/TXRDYb]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]

102
fpga/constraints/debug2.xdc
View File

@ -46,6 +46,7 @@ create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe7]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/hart/PCM[0]} {wallypipelinedsoc/hart/PCM[1]} {wallypipelinedsoc/hart/PCM[2]} {wallypipelinedsoc/hart/PCM[3]} {wallypipelinedsoc/hart/PCM[4]} {wallypipelinedsoc/hart/PCM[5]} {wallypipelinedsoc/hart/PCM[6]} {wallypipelinedsoc/hart/PCM[7]} {wallypipelinedsoc/hart/PCM[8]} {wallypipelinedsoc/hart/PCM[9]} {wallypipelinedsoc/hart/PCM[10]} {wallypipelinedsoc/hart/PCM[11]} {wallypipelinedsoc/hart/PCM[12]} {wallypipelinedsoc/hart/PCM[13]} {wallypipelinedsoc/hart/PCM[14]} {wallypipelinedsoc/hart/PCM[15]} {wallypipelinedsoc/hart/PCM[16]} {wallypipelinedsoc/hart/PCM[17]} {wallypipelinedsoc/hart/PCM[18]} {wallypipelinedsoc/hart/PCM[19]} {wallypipelinedsoc/hart/PCM[20]} {wallypipelinedsoc/hart/PCM[21]} {wallypipelinedsoc/hart/PCM[22]} {wallypipelinedsoc/hart/PCM[23]} {wallypipelinedsoc/hart/PCM[24]} {wallypipelinedsoc/hart/PCM[25]} {wallypipelinedsoc/hart/PCM[26]} {wallypipelinedsoc/hart/PCM[27]} {wallypipelinedsoc/hart/PCM[28]} {wallypipelinedsoc/hart/PCM[29]} {wallypipelinedsoc/hart/PCM[30]} {wallypipelinedsoc/hart/PCM[31]} {wallypipelinedsoc/hart/PCM[32]} {wallypipelinedsoc/hart/PCM[33]} {wallypipelinedsoc/hart/PCM[34]} {wallypipelinedsoc/hart/PCM[35]} {wallypipelinedsoc/hart/PCM[36]} {wallypipelinedsoc/hart/PCM[37]} {wallypipelinedsoc/hart/PCM[38]} {wallypipelinedsoc/hart/PCM[39]} {wallypipelinedsoc/hart/PCM[40]} {wallypipelinedsoc/hart/PCM[41]} {wallypipelinedsoc/hart/PCM[42]} {wallypipelinedsoc/hart/PCM[43]} {wallypipelinedsoc/hart/PCM[44]} {wallypipelinedsoc/hart/PCM[45]} {wallypipelinedsoc/hart/PCM[46]} {wallypipelinedsoc/hart/PCM[47]} {wallypipelinedsoc/hart/PCM[48]} {wallypipelinedsoc/hart/PCM[49]} {wallypipelinedsoc/hart/PCM[50]} {wallypipelinedsoc/hart/PCM[51]} {wallypipelinedsoc/hart/PCM[52]} {wallypipelinedsoc/hart/PCM[53]} {wallypipelinedsoc/hart/PCM[54]} {wallypipelinedsoc/hart/PCM[55]} {wallypipelinedsoc/hart/PCM[56]} {wallypipelinedsoc/hart/PCM[57]} {wallypipelinedsoc/hart/PCM[58]} {wallypipelinedsoc/hart/PCM[59]} {wallypipelinedsoc/hart/PCM[60]} {wallypipelinedsoc/hart/PCM[61]} {wallypipelinedsoc/hart/PCM[62]} {wallypipelinedsoc/hart/PCM[63]} ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe8]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
@ -467,3 +468,104 @@ create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe103]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103]
connect_debug_port u_ila_0/probe103 [get_nets [list wallypipelinedsoc/hart/ifu/icache/InstrReadF ]]
create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe104]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104]
connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[0]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[1]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[2]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[3]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[4]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[5]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[6]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[7]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[8]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[9]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[10]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[11]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[12]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[13]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[14]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[15]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[16]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[17]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[18]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[19]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[20]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[21]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[22]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[23]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[24]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[25]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[26]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[27]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[28]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[29]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[30]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[31]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[32]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[33]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[34]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[35]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[36]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[37]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[38]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[39]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[40]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[41]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[42]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[43]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[44]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[45]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[46]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[47]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[48]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[49]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[50]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[51]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[52]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[53]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[54]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[55]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[56]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[57]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[58]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[59]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[60]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[61]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[62]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[63]}]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe105]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105]
connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/hart/ebu/HRDATA[0]} {wallypipelinedsoc/hart/ebu/HRDATA[1]} {wallypipelinedsoc/hart/ebu/HRDATA[2]} {wallypipelinedsoc/hart/ebu/HRDATA[3]} {wallypipelinedsoc/hart/ebu/HRDATA[4]} {wallypipelinedsoc/hart/ebu/HRDATA[5]} {wallypipelinedsoc/hart/ebu/HRDATA[6]} {wallypipelinedsoc/hart/ebu/HRDATA[7]} {wallypipelinedsoc/hart/ebu/HRDATA[8]} {wallypipelinedsoc/hart/ebu/HRDATA[9]} {wallypipelinedsoc/hart/ebu/HRDATA[10]} {wallypipelinedsoc/hart/ebu/HRDATA[11]} {wallypipelinedsoc/hart/ebu/HRDATA[12]} {wallypipelinedsoc/hart/ebu/HRDATA[13]} {wallypipelinedsoc/hart/ebu/HRDATA[14]} {wallypipelinedsoc/hart/ebu/HRDATA[15]} {wallypipelinedsoc/hart/ebu/HRDATA[16]} {wallypipelinedsoc/hart/ebu/HRDATA[17]} {wallypipelinedsoc/hart/ebu/HRDATA[18]} {wallypipelinedsoc/hart/ebu/HRDATA[19]} {wallypipelinedsoc/hart/ebu/HRDATA[20]} {wallypipelinedsoc/hart/ebu/HRDATA[21]} {wallypipelinedsoc/hart/ebu/HRDATA[22]} {wallypipelinedsoc/hart/ebu/HRDATA[23]} {wallypipelinedsoc/hart/ebu/HRDATA[24]} {wallypipelinedsoc/hart/ebu/HRDATA[25]} {wallypipelinedsoc/hart/ebu/HRDATA[26]} {wallypipelinedsoc/hart/ebu/HRDATA[27]} {wallypipelinedsoc/hart/ebu/HRDATA[28]} {wallypipelinedsoc/hart/ebu/HRDATA[29]} {wallypipelinedsoc/hart/ebu/HRDATA[30]} {wallypipelinedsoc/hart/ebu/HRDATA[31]}]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe106]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106]
connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/hart/ebu/HWDATA[0]} {wallypipelinedsoc/hart/ebu/HWDATA[1]} {wallypipelinedsoc/hart/ebu/HWDATA[2]} {wallypipelinedsoc/hart/ebu/HWDATA[3]} {wallypipelinedsoc/hart/ebu/HWDATA[4]} {wallypipelinedsoc/hart/ebu/HWDATA[5]} {wallypipelinedsoc/hart/ebu/HWDATA[6]} {wallypipelinedsoc/hart/ebu/HWDATA[7]} {wallypipelinedsoc/hart/ebu/HWDATA[8]} {wallypipelinedsoc/hart/ebu/HWDATA[9]} {wallypipelinedsoc/hart/ebu/HWDATA[10]} {wallypipelinedsoc/hart/ebu/HWDATA[11]} {wallypipelinedsoc/hart/ebu/HWDATA[12]} {wallypipelinedsoc/hart/ebu/HWDATA[13]} {wallypipelinedsoc/hart/ebu/HWDATA[14]} {wallypipelinedsoc/hart/ebu/HWDATA[15]} {wallypipelinedsoc/hart/ebu/HWDATA[16]} {wallypipelinedsoc/hart/ebu/HWDATA[17]} {wallypipelinedsoc/hart/ebu/HWDATA[18]} {wallypipelinedsoc/hart/ebu/HWDATA[19]} {wallypipelinedsoc/hart/ebu/HWDATA[20]} {wallypipelinedsoc/hart/ebu/HWDATA[21]} {wallypipelinedsoc/hart/ebu/HWDATA[22]} {wallypipelinedsoc/hart/ebu/HWDATA[23]} {wallypipelinedsoc/hart/ebu/HWDATA[24]} {wallypipelinedsoc/hart/ebu/HWDATA[25]} {wallypipelinedsoc/hart/ebu/HWDATA[26]} {wallypipelinedsoc/hart/ebu/HWDATA[27]} {wallypipelinedsoc/hart/ebu/HWDATA[28]} {wallypipelinedsoc/hart/ebu/HWDATA[29]} {wallypipelinedsoc/hart/ebu/HWDATA[30]} {wallypipelinedsoc/hart/ebu/HWDATA[31]}]]
create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe107]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe107]
connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsoc/hart/ebu/HADDR[0]} {wallypipelinedsoc/hart/ebu/HADDR[1]} {wallypipelinedsoc/hart/ebu/HADDR[2]} {wallypipelinedsoc/hart/ebu/HADDR[3]} {wallypipelinedsoc/hart/ebu/HADDR[4]} {wallypipelinedsoc/hart/ebu/HADDR[5]} {wallypipelinedsoc/hart/ebu/HADDR[6]} {wallypipelinedsoc/hart/ebu/HADDR[7]} {wallypipelinedsoc/hart/ebu/HADDR[8]} {wallypipelinedsoc/hart/ebu/HADDR[9]} {wallypipelinedsoc/hart/ebu/HADDR[10]} {wallypipelinedsoc/hart/ebu/HADDR[11]} {wallypipelinedsoc/hart/ebu/HADDR[12]} {wallypipelinedsoc/hart/ebu/HADDR[13]} {wallypipelinedsoc/hart/ebu/HADDR[14]} {wallypipelinedsoc/hart/ebu/HADDR[15]} {wallypipelinedsoc/hart/ebu/HADDR[16]} {wallypipelinedsoc/hart/ebu/HADDR[17]} {wallypipelinedsoc/hart/ebu/HADDR[18]} {wallypipelinedsoc/hart/ebu/HADDR[19]} {wallypipelinedsoc/hart/ebu/HADDR[20]} {wallypipelinedsoc/hart/ebu/HADDR[21]} {wallypipelinedsoc/hart/ebu/HADDR[22]} {wallypipelinedsoc/hart/ebu/HADDR[23]} {wallypipelinedsoc/hart/ebu/HADDR[24]} {wallypipelinedsoc/hart/ebu/HADDR[25]} {wallypipelinedsoc/hart/ebu/HADDR[26]} {wallypipelinedsoc/hart/ebu/HADDR[27]} {wallypipelinedsoc/hart/ebu/HADDR[28]} {wallypipelinedsoc/hart/ebu/HADDR[29]} {wallypipelinedsoc/hart/ebu/HADDR[30]} {wallypipelinedsoc/hart/ebu/HADDR[31]}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe108]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe108]
connect_debug_port u_ila_0/probe108 [get_nets [list {wallypipelinedsoc/hart/ebu/HREADY}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe109]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe109]
connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsoc/hart/ebu/HRESP}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe110]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe110]
connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsoc/hart/ebu/HWRITE}]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe111]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe111]
connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsoc/hart/ebu/HSIZE[0]} {wallypipelinedsoc/hart/ebu/HSIZE[1]} {wallypipelinedsoc/hart/ebu/HSIZE[2]}]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe112]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe112]
connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsoc/hart/ebu/HBURST[0]} {wallypipelinedsoc/hart/ebu/HBURST[1]} {wallypipelinedsoc/hart/ebu/HBURST[2]}]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe113]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe113]
connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsoc/hart/ebu/HPROT[0]} {wallypipelinedsoc/hart/ebu/HPROT[1]} {wallypipelinedsoc/hart/ebu/HPROT[2]} {wallypipelinedsoc/hart/ebu/HPROT[3]}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe114]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe114]
connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/hart/ebu/HMASTLOCK}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe115]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe115]
connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsoc/hart/priv/InterruptM}]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe116]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe116]
connect_debug_port u_ila_0/probe116 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/ITLBMissF]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe117]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe117]
connect_debug_port u_ila_0/probe117 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/DTLBMissM]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe118]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe118]
connect_debug_port u_ila_0/probe118 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/ITLBWriteF]]
create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe119]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119]
connect_debug_port u_ila_0/probe119 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/DTLBWriteM]]
create_debug_port u_ila_0 probe
set_property port_width 11 [get_debug_ports u_ila_0/probe120]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120]
connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/hart/lsu/hptw/WalkerState[0]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[1]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[2]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[3]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[4]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[5]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[6]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[7]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[8]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[9]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[10]}]]
create_debug_port u_ila_0 probe
set_property port_width 56 [get_debug_ports u_ila_0/probe121]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121]
connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/hart/lsu/MemPAdrM[0]} {wallypipelinedsoc/hart/lsu/MemPAdrM[1]} {wallypipelinedsoc/hart/lsu/MemPAdrM[2]} {wallypipelinedsoc/hart/lsu/MemPAdrM[3]} {wallypipelinedsoc/hart/lsu/MemPAdrM[4]} {wallypipelinedsoc/hart/lsu/MemPAdrM[5]} {wallypipelinedsoc/hart/lsu/MemPAdrM[6]} {wallypipelinedsoc/hart/lsu/MemPAdrM[7]} {wallypipelinedsoc/hart/lsu/MemPAdrM[8]} {wallypipelinedsoc/hart/lsu/MemPAdrM[9]} {wallypipelinedsoc/hart/lsu/MemPAdrM[10]} {wallypipelinedsoc/hart/lsu/MemPAdrM[11]} {wallypipelinedsoc/hart/lsu/MemPAdrM[12]} {wallypipelinedsoc/hart/lsu/MemPAdrM[13]} {wallypipelinedsoc/hart/lsu/MemPAdrM[14]} {wallypipelinedsoc/hart/lsu/MemPAdrM[15]} {wallypipelinedsoc/hart/lsu/MemPAdrM[16]} {wallypipelinedsoc/hart/lsu/MemPAdrM[17]} {wallypipelinedsoc/hart/lsu/MemPAdrM[18]} {wallypipelinedsoc/hart/lsu/MemPAdrM[19]} {wallypipelinedsoc/hart/lsu/MemPAdrM[20]} {wallypipelinedsoc/hart/lsu/MemPAdrM[21]} {wallypipelinedsoc/hart/lsu/MemPAdrM[22]} {wallypipelinedsoc/hart/lsu/MemPAdrM[23]} {wallypipelinedsoc/hart/lsu/MemPAdrM[24]} {wallypipelinedsoc/hart/lsu/MemPAdrM[25]} {wallypipelinedsoc/hart/lsu/MemPAdrM[26]} {wallypipelinedsoc/hart/lsu/MemPAdrM[27]} {wallypipelinedsoc/hart/lsu/MemPAdrM[28]} {wallypipelinedsoc/hart/lsu/MemPAdrM[29]} {wallypipelinedsoc/hart/lsu/MemPAdrM[30]} {wallypipelinedsoc/hart/lsu/MemPAdrM[31]} {wallypipelinedsoc/hart/lsu/MemPAdrM[32]} {wallypipelinedsoc/hart/lsu/MemPAdrM[33]} {wallypipelinedsoc/hart/lsu/MemPAdrM[34]} {wallypipelinedsoc/hart/lsu/MemPAdrM[35]} {wallypipelinedsoc/hart/lsu/MemPAdrM[36]} {wallypipelinedsoc/hart/lsu/MemPAdrM[37]} {wallypipelinedsoc/hart/lsu/MemPAdrM[38]} {wallypipelinedsoc/hart/lsu/MemPAdrM[39]} {wallypipelinedsoc/hart/lsu/MemPAdrM[40]} {wallypipelinedsoc/hart/lsu/MemPAdrM[41]} {wallypipelinedsoc/hart/lsu/MemPAdrM[42]} {wallypipelinedsoc/hart/lsu/MemPAdrM[43]} {wallypipelinedsoc/hart/lsu/MemPAdrM[44]} {wallypipelinedsoc/hart/lsu/MemPAdrM[45]} {wallypipelinedsoc/hart/lsu/MemPAdrM[46]} {wallypipelinedsoc/hart/lsu/MemPAdrM[47]} {wallypipelinedsoc/hart/lsu/MemPAdrM[48]} {wallypipelinedsoc/hart/lsu/MemPAdrM[49]} {wallypipelinedsoc/hart/lsu/MemPAdrM[50]} {wallypipelinedsoc/hart/lsu/MemPAdrM[51]} {wallypipelinedsoc/hart/lsu/MemPAdrM[52]} {wallypipelinedsoc/hart/lsu/MemPAdrM[53]} {wallypipelinedsoc/hart/lsu/MemPAdrM[54]} {wallypipelinedsoc/hart/lsu/MemPAdrM[55]} ]]
create_debug_port u_ila_0 probe
set_property port_width 56 [get_debug_ports u_ila_0/probe122]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe122]
connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/hart/ifu/PCPFmmu[0]} {wallypipelinedsoc/hart/ifu/PCPFmmu[1]} {wallypipelinedsoc/hart/ifu/PCPFmmu[2]} {wallypipelinedsoc/hart/ifu/PCPFmmu[3]} {wallypipelinedsoc/hart/ifu/PCPFmmu[4]} {wallypipelinedsoc/hart/ifu/PCPFmmu[5]} {wallypipelinedsoc/hart/ifu/PCPFmmu[6]} {wallypipelinedsoc/hart/ifu/PCPFmmu[7]} {wallypipelinedsoc/hart/ifu/PCPFmmu[8]} {wallypipelinedsoc/hart/ifu/PCPFmmu[9]} {wallypipelinedsoc/hart/ifu/PCPFmmu[10]} {wallypipelinedsoc/hart/ifu/PCPFmmu[11]} {wallypipelinedsoc/hart/ifu/PCPFmmu[12]} {wallypipelinedsoc/hart/ifu/PCPFmmu[13]} {wallypipelinedsoc/hart/ifu/PCPFmmu[14]} {wallypipelinedsoc/hart/ifu/PCPFmmu[15]} {wallypipelinedsoc/hart/ifu/PCPFmmu[16]} {wallypipelinedsoc/hart/ifu/PCPFmmu[17]} {wallypipelinedsoc/hart/ifu/PCPFmmu[18]} {wallypipelinedsoc/hart/ifu/PCPFmmu[19]} {wallypipelinedsoc/hart/ifu/PCPFmmu[20]} {wallypipelinedsoc/hart/ifu/PCPFmmu[21]} {wallypipelinedsoc/hart/ifu/PCPFmmu[22]} {wallypipelinedsoc/hart/ifu/PCPFmmu[23]} {wallypipelinedsoc/hart/ifu/PCPFmmu[24]} {wallypipelinedsoc/hart/ifu/PCPFmmu[25]} {wallypipelinedsoc/hart/ifu/PCPFmmu[26]} {wallypipelinedsoc/hart/ifu/PCPFmmu[27]} {wallypipelinedsoc/hart/ifu/PCPFmmu[28]} {wallypipelinedsoc/hart/ifu/PCPFmmu[29]} {wallypipelinedsoc/hart/ifu/PCPFmmu[30]} {wallypipelinedsoc/hart/ifu/PCPFmmu[31]} {wallypipelinedsoc/hart/ifu/PCPFmmu[32]} {wallypipelinedsoc/hart/ifu/PCPFmmu[33]} {wallypipelinedsoc/hart/ifu/PCPFmmu[34]} {wallypipelinedsoc/hart/ifu/PCPFmmu[35]} {wallypipelinedsoc/hart/ifu/PCPFmmu[36]} {wallypipelinedsoc/hart/ifu/PCPFmmu[37]} {wallypipelinedsoc/hart/ifu/PCPFmmu[38]} {wallypipelinedsoc/hart/ifu/PCPFmmu[39]} {wallypipelinedsoc/hart/ifu/PCPFmmu[40]} {wallypipelinedsoc/hart/ifu/PCPFmmu[41]} {wallypipelinedsoc/hart/ifu/PCPFmmu[42]} {wallypipelinedsoc/hart/ifu/PCPFmmu[43]} {wallypipelinedsoc/hart/ifu/PCPFmmu[44]} {wallypipelinedsoc/hart/ifu/PCPFmmu[45]} {wallypipelinedsoc/hart/ifu/PCPFmmu[46]} {wallypipelinedsoc/hart/ifu/PCPFmmu[47]} {wallypipelinedsoc/hart/ifu/PCPFmmu[48]} {wallypipelinedsoc/hart/ifu/PCPFmmu[49]} {wallypipelinedsoc/hart/ifu/PCPFmmu[50]} {wallypipelinedsoc/hart/ifu/PCPFmmu[51]} {wallypipelinedsoc/hart/ifu/PCPFmmu[52]} {wallypipelinedsoc/hart/ifu/PCPFmmu[53]} {wallypipelinedsoc/hart/ifu/PCPFmmu[54]} {wallypipelinedsoc/hart/ifu/PCPFmmu[55]} ]]

6
fpga/generator/wally.tcl
View File

@ -69,9 +69,9 @@ open_run impl_1
exec mkdir -p sim/
exec rm -rf sim/*
write_verilog -force -mode funcsim sim/funcsim.v
write_verilog -force -mode timesim sim/timesim.v
write_sdf -force sim/timesim.sdf
write_verilog -force -mode funcsim sim/imp-funcsim.v
write_verilog -force -mode timesim sim/imp-timesim.v
write_sdf -force sim/imp-timesim.sdf
# reports
check_timing -file reports/imp_check_timing.rpt

0
wally-pipelined/linux-testgen/linux-testvectors/convert2bin.py → tests/linux-testgen/linux-testvectors/convert2bin.py
View File

0
wally-pipelined/linux-testgen/qemu-build-instructions.md → tests/linux-testgen/qemu-build-instructions.md
View File

0
wally-pipelined/linux-testgen/wallyVirtIO.patch → tests/linux-testgen/wallyVirtIO.patch
View File

402
wally-pipelined/regression/linux-wave.do
View File

@ -5,22 +5,6 @@ add wave -noupdate /testbench/reset
add wave -noupdate /testbench/reset_ext
add wave -noupdate -radix unsigned /testbench/InstrCountW
add wave -noupdate /testbench/dut/hart/SATP_REGW
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
@ -69,31 +53,30 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ieu/c/In
add wave -noupdate -expand -group {Execution Stage} /testbench/textE
add wave -noupdate -expand -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
add wave -noupdate -expand -group {Memory Stage} /testbench/textM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/IEUAdrM
add wave -noupdate -expand -group {WriteBack stage} /testbench/checkInstrW
add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrValidW
add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
add wave -noupdate -expand -group {WriteBack stage} /testbench/ExpectedPCW
add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrW
add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrWName
add wave -noupdate -expand -group {WriteBack stage} /testbench/textW
add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW
add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW
add wave -noupdate -group {WriteBack stage} /testbench/PCW
add wave -noupdate -group {WriteBack stage} /testbench/ExpectedPCW
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
add wave -noupdate -group {WriteBack stage} /testbench/textW
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
@ -139,30 +122,22 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/FlagsE
add wave -noupdate -group alu -divider internals
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
@ -180,15 +155,6 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivE
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/W64E
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallM
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallW
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
@ -239,133 +205,141 @@ add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3
add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srca
add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srcb
add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/width
add wave -noupdate -expand -group lsu -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultF
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultRaw
add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrE
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/RAdr
add wave -noupdate -expand -group lsu -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
@ -404,7 +378,6 @@ add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pm
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
@ -414,27 +387,9 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /test
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
add wave -noupdate -group csr -color Gray90 -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIE_REGW
add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/MIP_REGW
add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MSTATUS_REGW
add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW
add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/MTVEC_REGW
add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW
add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW
add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW
add wave -noupdate -group csr -expand -group machine -color Brown /testbench/dut/hart/priv/PrivilegeModeW
add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/STVEC_REGW
add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/STVAL
add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSE_REGW
add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIP_REGW
add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIE_REGW
add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
@ -504,7 +459,6 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/hart/FlushW
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/priv/trap/InstrValidM
add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM
add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM
@ -518,19 +472,27 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/textW
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM
add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/PrivilegedNextPCM
add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedVectoredTrapVector
add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedTrapVector
add wave -noupdate /testbench/dut/hart/ifu/PCCorrectE
add wave -noupdate /testbench/dut/hart/ifu/PCSrcE
add wave -noupdate /testbench/dut/hart/ieu/c/BranchTakenE
add wave -noupdate /testbench/dut/hart/ieu/c/BranchE
add wave -noupdate /testbench/dut/hart/ifu/PCTargetE
add wave -noupdate /testbench/dut/hart/ifu/PCLinkE
add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBSizeM
add wave -noupdate /testbench/dut/hart/ifu/PCF
add wave -noupdate /testbench/dut/hart/priv/priv/BreakpointFaultM
add wave -noupdate /testbench/dut/hart/priv/priv/DTLBLoadPageFaultM
add wave -noupdate /testbench/dut/hart/priv/priv/DTLBStorePageFaultM
add wave -noupdate /testbench/dut/hart/priv/priv/ebreakM
add wave -noupdate /testbench/dut/hart/priv/priv/EcallFaultM
add wave -noupdate /testbench/dut/hart/priv/priv/ecallM
add wave -noupdate /testbench/dut/hart/priv/priv/ExceptionM
add wave -noupdate /testbench/dut/hart/priv/priv/IllegalCSRAccessM
add wave -noupdate /testbench/dut/hart/priv/priv/IllegalFPUInstrM
add wave -noupdate /testbench/dut/hart/priv/priv/IllegalIEUInstrFaultM
add wave -noupdate /testbench/dut/hart/priv/priv/InstrAccessFaultM
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 23} {14157765 ns} 0} {{Cursor 3} {29725 ns} 1}
quietly wave cursor active 1
WaveRestoreCursors {{Cursor 23} {14157765 ns} 0} {{Cursor 3} {29725 ns} 1} {{Cursor 5} {209653 ns} 0}
quietly wave cursor active 3
configure wave -namecolwidth 250
configure wave -valuecolwidth 314
configure wave -justifyvalue left
@ -545,4 +507,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {14157667 ns} {14157811 ns}
WaveRestoreZoom {211096 ns} {211182 ns}

279
wally-pipelined/regression/wave.do
View File

@ -4,7 +4,7 @@ add wave -noupdate /testbench/clk
add wave -noupdate /testbench/reset
add wave -noupdate /testbench/test
add wave -noupdate /testbench/memfilename
add wave -noupdate /testbench/dut/hart/SATP_REGW
add wave -noupdate /testbench/dut/hart/lsu/SATP_REGW
add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
add wave -noupdate -group {Execution Stage} /testbench/InstrEName
add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
@ -15,41 +15,41 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/IEUAdrM
add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM
add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
@ -103,22 +103,22 @@ add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
add wave -noupdate -group {instruction pipeline} /testbench/InstrW
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -group {Decode Stage} /testbench/InstrDName
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
@ -151,12 +151,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -group PCS /testbench/dut/hart/PCF
add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
add wave -noupdate -group PCS /testbench/dut/hart/PCE
add wave -noupdate -group PCS /testbench/dut/hart/PCM
add wave -noupdate -group PCS /testbench/PCW
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
add wave -noupdate -expand -group PCS /testbench/PCW
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcAE
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcBE
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
@ -168,86 +168,86 @@ add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/WayHit
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/VictimWay
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteWordEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/SetValid}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/SetValid}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/DirtyBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SelAdr
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/RAdr
add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/FinalInstrRawF
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
add wave -noupdate -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/WayHit
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/VictimWay
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteWordEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/SetValid}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/SetValid}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/DirtyBits}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/SelAdr
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/RAdr
add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/FinalInstrRawF
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
@ -269,8 +269,10 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
add wave -noupdate -expand -group lsu /testbench/dut/hart/hzu/LSUStall
add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelHPTW
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
@ -422,7 +424,8 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group typ
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/MIP_REGW
add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
@ -496,8 +499,6 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
add wave -noupdate /testbench/dut/hart/lsu/CurrState
add wave -noupdate /testbench/dut/hart/lsu/InterlockStall
add wave -noupdate /testbench/dut/hart/ifu/icache/PCNextF
add wave -noupdate /testbench/dut/hart/ifu/icache/PCPF
add wave -noupdate /testbench/dut/hart/lsu/WalkerInstrPageFaultF
@ -506,8 +507,8 @@ add wave -noupdate /testbench/dut/hart/lsu/dcache/RAdr
add wave -noupdate /testbench/dut/hart/lsu/dcache/SelAdrM
add wave -noupdate /testbench/dut/hart/lsu/SelReplayCPURequest
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 6} {24475 ns} 1} {{Cursor 2} {22501 ns} 1} {{Cursor 3} {3615 ns} 0}
quietly wave cursor active 3
WaveRestoreCursors {{Cursor 6} {26646 ns} 1} {{Cursor 2} {70866 ns} 0} {{Cursor 3} {24171 ns} 1}
quietly wave cursor active 2
configure wave -namecolwidth 250
configure wave -valuecolwidth 297
configure wave -justifyvalue left
@ -522,4 +523,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {3453 ns} {3729 ns}
WaveRestoreZoom {70741 ns} {70973 ns}

6
wally-pipelined/src/cache/dcache.sv vendored
View File

@ -28,7 +28,7 @@
module dcache
(input logic clk,
input logic reset,
input logic StallWtoDCache,
input logic CPUBusy,
// cpu side
input logic [1:0] MemRWM,
@ -53,7 +53,6 @@ module dcache
input logic CacheableM,
// from ptw
input logic IgnoreRequest,
output logic MemAfterIWalkDone,
// ahb side
(* mark_debug = "true" *)output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
(* mark_debug = "true" *)output logic AHBRead,
@ -347,7 +346,7 @@ module dcache
.AtomicM,
.ExceptionM,
.PendingInterruptM,
.StallWtoDCache,
.CPUBusy,
.CacheableM,
.IgnoreRequest,
.AHBAck, // from ahb
@ -358,7 +357,6 @@ module dcache
.CommittedM,
.DCacheMiss,
.DCacheAccess,
.MemAfterIWalkDone,
.AHBRead,
.AHBWrite,
.SelAdrM,

25
wally-pipelined/src/cache/dcachefsm.sv vendored
View File

@ -35,7 +35,7 @@ module dcachefsm
// hazard inputs
input logic ExceptionM,
input logic PendingInterruptM,
input logic StallWtoDCache,
input logic CPUBusy,
input logic CacheableM,
// hptw inputs
input logic IgnoreRequest,
@ -53,8 +53,6 @@ module dcachefsm
// counter outputs
output logic DCacheMiss,
output logic DCacheAccess,
// hptw outputs
output logic MemAfterIWalkDone,
// Bus outputs
output logic AHBRead,
output logic AHBWrite,
@ -137,7 +135,6 @@ module dcachefsm
SelUncached = 1'b0;
SelEvict = 1'b0;
LRUWriteEn = 1'b0;
MemAfterIWalkDone = 1'b0;
SelFlush = 1'b0;
FlushAdrCntEn = 1'b0;
FlushWayCntEn = 1'b0;
@ -185,7 +182,7 @@ module dcachefsm
SelAdrM = 2'b10;
DCacheStall = 1'b0;
if(StallWtoDCache) begin
if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO;
SelAdrM = 2'b10;
end
@ -201,7 +198,7 @@ module dcachefsm
DCacheStall = 1'b0;
LRUWriteEn = 1'b1;
if(StallWtoDCache) begin
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10;
end
@ -217,7 +214,7 @@ module dcachefsm
SetDirty = 1'b1;
LRUWriteEn = 1'b1;
if(StallWtoDCache) begin
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10;
end
@ -310,7 +307,7 @@ module dcachefsm
LRUWriteEn = 1'b0;
if(&MemRWM & AtomicM[1]) begin // amo write
SelAdrM = 2'b10;
if(StallWtoDCache) begin
if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO;
end
else begin
@ -321,7 +318,7 @@ module dcachefsm
end
end else begin
LRUWriteEn = 1'b1;
if(StallWtoDCache) begin
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10;
end
@ -337,7 +334,7 @@ module dcachefsm
SelAdrM = 2'b10;
CommittedM = 1'b1;
LRUWriteEn = 1'b1;
if(StallWtoDCache) begin
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10;
end
@ -364,7 +361,7 @@ module dcachefsm
STATE_CPU_BUSY: begin
CommittedM = 1'b1;
SelAdrM = 2'b00;
if(StallWtoDCache) begin
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10;
end
@ -379,7 +376,7 @@ module dcachefsm
SRAMWordWriteEnableM = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0;
if(StallWtoDCache) begin
if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO;
end
else begin
@ -415,7 +412,7 @@ module dcachefsm
STATE_UNCACHED_WRITE_DONE: begin
CommittedM = 1'b1;
SelAdrM = 2'b00;
if(StallWtoDCache) begin
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10;
end
@ -428,7 +425,7 @@ module dcachefsm
CommittedM = 1'b1;
SelUncached = 1'b1;
SelAdrM = 2'b00;
if(StallWtoDCache) begin
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
SelAdrM = 2'b10;
end

28
wally-pipelined/src/ebu/ahblite.sv
View File

@ -53,21 +53,21 @@ module ahblite (
input logic [1:0] MemSizeM, // *** remove
output logic DCfromAHBAck,
// AHB-Lite external signals
input logic [`AHBW-1:0] HRDATA,
input logic HREADY, HRESP,
output logic HCLK, HRESETn,
output logic [31:0] HADDR,
output logic [`AHBW-1:0] HWDATA,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
output logic [3:0] HPROT,
output logic [1:0] HTRANS,
output logic HMASTLOCK,
(* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA,
(* mark_debug = "true" *) input logic HREADY, HRESP,
(* mark_debug = "true" *) output logic HCLK, HRESETn,
(* mark_debug = "true" *) output logic [31:0] HADDR,
(* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA,
(* mark_debug = "true" *) output logic HWRITE,
(* mark_debug = "true" *) output logic [2:0] HSIZE,
(* mark_debug = "true" *) output logic [2:0] HBURST,
(* mark_debug = "true" *) output logic [3:0] HPROT,
(* mark_debug = "true" *) output logic [1:0] HTRANS,
(* mark_debug = "true" *) output logic HMASTLOCK,
// Delayed signals for writes
output logic [2:0] HADDRD,
output logic [3:0] HSIZED,
output logic HWRITED
(* mark_debug = "true" *) output logic [2:0] HADDRD,
(* mark_debug = "true" *) output logic [3:0] HSIZED,
(* mark_debug = "true" *) output logic HWRITED
);
logic GrantData;

4
wally-pipelined/src/ifu/ifu.sv
View File

@ -33,7 +33,7 @@ module ifu (
// Fetch
input logic [`XLEN-1:0] InstrInF,
input logic InstrAckF,
output logic [`XLEN-1:0] PCF,
(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
output logic [`PA_BITS-1:0] InstrPAdrF,
output logic InstrReadF,
output logic ICacheStallF,
@ -101,7 +101,7 @@ module ifu (
logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
(* mark_debug = "true" *) logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
logic [`XLEN+1:0] PCFExt;
generate

4
wally-pipelined/src/lsu/lrsc.sv
View File

@ -29,7 +29,7 @@
module lrsc
(
input logic clk, reset,
input logic FlushW, StallWtoDCache,
input logic FlushW, CPUBusy,
input logic MemReadM,
input logic [1:0] MemRWMtoLRSC,
output logic [1:0] MemRWMtoDCache,
@ -57,7 +57,7 @@ module lrsc
end
flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoDCache, SquashSCM, SquashSCW);
flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW);
end else begin // Atomic operations not supported
assign SquashSCW = 0;
assign MemRWMtoDCache = MemRWMtoLRSC;

231
wally-pipelined/src/lsu/lsu.sv
View File

@ -27,7 +27,6 @@
`include "wally-config.vh"
// *** Ross Thompson amo misalignment check?
module lsu
(
input logic clk, reset,
@ -50,7 +49,7 @@ module lsu
// address and write data
input logic [`XLEN-1:0] IEUAdrE,
output logic [`XLEN-1:0] IEUAdrM,
(* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM,
input logic [`XLEN-1:0] WriteDataM,
output logic [`XLEN-1:0] ReadDataM,
@ -93,15 +92,13 @@ module lsu
);
logic DTLBPageFaultM;
logic DataMisalignedM;
logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache
logic [`XLEN+1:0] IEUAdrExtM;
logic DTLBMissM;
logic DTLBWriteM;
logic HPTWStall;
logic [`PA_BITS-1:0] TranslationPAdr;
logic [`PA_BITS-1:0] HPTWAdr;
logic HPTWRead;
logic [1:0] MemRWMtoDCache;
logic [1:0] MemRWMtoLRSC;
@ -109,19 +106,19 @@ module lsu
logic [1:0] AtomicMtoDCache;
logic [`PA_BITS-1:0] MemPAdrNoTranslate;
logic [11:0] MemAdrE, MemAdrE_RENAME;
logic StallWtoDCache;
logic CPUBusy;
logic MemReadM;
logic DataMisalignedMfromDCache;
logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB.
logic DataMisalignedM;
logic DCacheStall;
logic CacheableM;
logic CacheableMtoDCache;
logic SelPTW;
logic SelHPTW;
logic [2:0] HPTWSize;
logic CommittedMfromDCache;
logic PendingInterruptMtoDCache;
// logic FlushWtoDCache;
logic WalkerPageFaultM;
logic AnyCPUReqM;
@ -141,7 +138,6 @@ module lsu
logic WalkerInstrPageFaultRaw;
logic IgnoreRequest;
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
always_ff @(posedge clk)
@ -150,73 +146,27 @@ module lsu
always_comb begin
case(CurrState)
STATE_T0_READY: begin
if(~ITLBMissF & DTLBMissM & AnyCPUReqM) begin
NextState = STATE_T3_DTLB_MISS;
end
else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) begin
NextState = STATE_T4_ITLB_MISS;
end
else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) begin
NextState = STATE_T5_ITLB_MISS;
end
else if(ITLBMissF & DTLBMissM & AnyCPUReqM) begin
NextState = STATE_T7_DITLB_MISS;
end else begin
NextState = STATE_T0_READY;
end
end
STATE_T0_REPLAY: begin
if(DCacheStall) begin
NextState = STATE_T0_REPLAY;
end else begin
NextState = STATE_T0_READY;
end
end
STATE_T3_DTLB_MISS: begin
if(WalkerLoadPageFaultM | WalkerStorePageFaultM) begin
NextState = STATE_T0_READY;
end else if(DTLBWriteM) begin
NextState = STATE_T0_REPLAY;
end else begin
NextState = STATE_T3_DTLB_MISS;
end
end
STATE_T4_ITLB_MISS: begin
if(WalkerInstrPageFaultRaw | ITLBWriteF) begin
NextState = STATE_T0_READY;
end else begin
NextState = STATE_T4_ITLB_MISS;
end
end
STATE_T5_ITLB_MISS: begin
if(ITLBWriteF) begin
NextState = STATE_T0_REPLAY;
end else if(WalkerInstrPageFaultRaw) begin
NextState = STATE_T0_FAULT_REPLAY;
end else begin
NextState = STATE_T5_ITLB_MISS;
end
end
STATE_T0_FAULT_REPLAY: begin
if(DCacheStall) begin
NextState = STATE_T0_FAULT_REPLAY;
end else begin
NextState = STATE_T0_READY;
end
end
STATE_T7_DITLB_MISS: begin
if(WalkerStorePageFaultM | WalkerLoadPageFaultM) begin
NextState = STATE_T0_READY;
end else if(DTLBWriteM) begin
NextState = STATE_T5_ITLB_MISS;
end else begin
NextState = STATE_T7_DITLB_MISS;
end
end
default: begin
NextState = STATE_T0_READY;
end
STATE_T0_READY: if(~ITLBMissF & DTLBMissM & AnyCPUReqM) NextState = STATE_T3_DTLB_MISS;
else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) NextState = STATE_T4_ITLB_MISS;
else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) NextState = STATE_T5_ITLB_MISS;
else if(ITLBMissF & DTLBMissM & AnyCPUReqM) NextState = STATE_T7_DITLB_MISS;
else NextState = STATE_T0_READY;
STATE_T0_REPLAY: if(DCacheStall) NextState = STATE_T0_REPLAY;
else NextState = STATE_T0_READY;
STATE_T3_DTLB_MISS: if(WalkerLoadPageFaultM | WalkerStorePageFaultM) NextState = STATE_T0_READY;
else if(DTLBWriteM) NextState = STATE_T0_REPLAY;
else NextState = STATE_T3_DTLB_MISS;
STATE_T4_ITLB_MISS: if(WalkerInstrPageFaultRaw | ITLBWriteF) NextState = STATE_T0_READY;
else NextState = STATE_T4_ITLB_MISS;
STATE_T5_ITLB_MISS: if(ITLBWriteF) NextState = STATE_T0_REPLAY;
else if(WalkerInstrPageFaultRaw) NextState = STATE_T0_FAULT_REPLAY;
else NextState = STATE_T5_ITLB_MISS;
STATE_T0_FAULT_REPLAY: if(DCacheStall) NextState = STATE_T0_FAULT_REPLAY;
else NextState = STATE_T0_READY;
STATE_T7_DITLB_MISS: if(WalkerStorePageFaultM | WalkerLoadPageFaultM) NextState = STATE_T0_READY;
else if(DTLBWriteM) NextState = STATE_T5_ITLB_MISS;
else NextState = STATE_T7_DITLB_MISS;
default: NextState = STATE_T0_READY;
endcase
end // always_comb
@ -236,7 +186,8 @@ module lsu
STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1;
STATE_T3_DTLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1;
STATE_T4_ITLB_MISS: if (~WalkerInstrPageFaultRaw) InterlockStall = 1'b1;
STATE_T5_ITLB_MISS: if (~WalkerInstrPageFaultRaw) InterlockStall = 1'b1;
STATE_T5_ITLB_MISS: InterlockStall = 1'b1;
//STATE_T0_FAULT_REPLAY: if (~WalkerInstrPageFaultF) InterlockStall = 1'b1;
STATE_T7_DITLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1;
default: InterlockStall = 1'b0;
endcase
@ -244,8 +195,8 @@ module lsu
// When replaying CPU memory request after PTW select the IEUAdrM for correct address.
assign SelReplayCPURequest = NextState == STATE_T0_REPLAY;
assign SelPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
assign SelReplayCPURequest = (NextState == STATE_T0_REPLAY) | (NextState == STATE_T0_FAULT_REPLAY);
assign SelHPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
(CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
assign IgnoreRequest = CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM);
@ -256,93 +207,71 @@ module lsu
// *** add generate to conditionally create hptw, lsuArb, and mmu
// based on `MEM_VIRTMEM
hptw hptw(.clk(clk),
.reset(reset),
.SATP_REGW(SATP_REGW),
.PCF(PCF),
.IEUAdrM(IEUAdrM),
hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
.ITLBMissF(ITLBMissF & ~PendingInterruptM),
.DTLBMissM(DTLBMissM & ~PendingInterruptM),
.MemRWM(MemRWM),
.PTE(PTE),
.PageType,
.ITLBWriteF(ITLBWriteF),
.DTLBWriteM(DTLBWriteM),
.MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
.HPTWReadPTE(ReadDataM),
.DCacheStall(DCacheStall),
.TranslationPAdr,
.HPTWRead(HPTWRead),
.HPTWStall,
.AnyCPUReqM,
.MemAfterIWalkDone,
.DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM,
.WalkerInstrPageFaultF(WalkerInstrPageFaultRaw),
.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
.WalkerStorePageFaultM(WalkerStorePageFaultM));
.WalkerLoadPageFaultM, .WalkerStorePageFaultM);
assign LSUStall = DCacheStall | InterlockStall;
assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
// arbiter between IEU and hptw
lsuArb arbiter(.clk(clk),
// HPTW connection
.SelPTW,
.HPTWRead(HPTWRead),
.TranslationPAdrE(TranslationPAdr),
// CPU connection
.MemRWM(MemRWM),
.Funct3M(Funct3M),
.AtomicM(AtomicM),
.IEUAdrM(IEUAdrM),
.IEUAdrE(IEUAdrE[11:0]),
.CommittedM(CommittedM),
.PendingInterruptM(PendingInterruptM),
.StallW(StallW),
.DataMisalignedM(DataMisalignedM),
// DCACHE
.DisableTranslation(DisableTranslation),
.MemRWMtoLRSC(MemRWMtoLRSC),
.Funct3MtoDCache(Funct3MtoDCache),
.AtomicMtoDCache(AtomicMtoDCache),
.MemPAdrNoTranslate(MemPAdrNoTranslate),
.MemAdrE(MemAdrE),
.StallWtoDCache(StallWtoDCache),
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
.CommittedMfromDCache(CommittedMfromDCache),
.PendingInterruptMtoDCache(PendingInterruptMtoDCache),
.DCacheStall(DCacheStall));
// multiplex the outputs to LSU
assign MemRWMtoLRSC = SelHPTW ? {HPTWRead, 1'b0} : MemRWM;
mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, Funct3MtoDCache);
// this is for the d cache SRAM.
// turns out because we cannot pipeline hptw requests we don't need this register
//flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle
assign AtomicMtoDCache = SelHPTW ? 2'b00 : AtomicM;
assign IEUAdrExtM = {2'b00, IEUAdrM};
assign MemPAdrNoTranslate = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0];
assign MemAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0];
assign CPUBusy = SelHPTW ? 1'b0 : StallW;
// always block interrupts when using the hardware page table walker.
assign CommittedM = SelHPTW ? 1'b1 : CommittedMfromDCache;
assign PendingInterruptMtoDCache = SelHPTW ? 1'b0 : PendingInterruptM;
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
.PrivilegeModeW, .DisableTranslation(DisableTranslation),
.PrivilegeModeW, .DisableTranslation(SelHPTW),
.PAdr(MemPAdrNoTranslate),
.VAdr(IEUAdrM),
.Size(Funct3MtoDCache[1:0]),
.PTE(PTE),
.PTE,
.PageTypeWriteVal(PageType),
.TLBWrite(DTLBWriteM),
.TLBFlush(DTLBFlushM),
.PhysicalAddress(MemPAdrM),
.TLBMiss(DTLBMissM),
.Cacheable(CacheableM),
.Idempotent(),
.AtomicAllowed(),
.Idempotent(), .AtomicAllowed(),
.TLBPageFault(DTLBPageFaultM),
.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM,
.AtomicAccessM(1'b0), .ExecuteAccessF(1'b0),
.WriteAccessM(MemRWMtoLRSC[0]), .ReadAccessM(MemRWMtoLRSC[1]),
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
//.AtomicAccessM(AtomicMaskedM[1]),
); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
// Move generate from lrsc to outside this module.
assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
lrsc lrsc(.clk, .reset, .FlushW, .StallWtoDCache, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM,
lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM,
.SquashSCW, .MemRWMtoDCache);
// *** BUG, this is most likely wrong
assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM;
assign CacheableMtoDCache = SelHPTW ? 1'b1 : CacheableM;
// Specify which type of page fault is occurring
@ -351,17 +280,18 @@ module lsu
assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLRSC[0];
// Determine if an Unaligned access is taking place
// hptw guarantees alignment, only check inputs from IEU.
always_comb
case(Funct3MtoDCache[1:0])
2'b00: DataMisalignedMfromDCache = 0; // lb, sb, lbu
2'b01: DataMisalignedMfromDCache = MemPAdrNoTranslate[0]; // lh, sh, lhu
2'b10: DataMisalignedMfromDCache = MemPAdrNoTranslate[1] | MemPAdrNoTranslate[0]; // lw, sw, flw, fsw, lwu
2'b11: DataMisalignedMfromDCache = |MemPAdrNoTranslate[2:0]; // ld, sd, fld, fsd
case(Funct3M[1:0])
2'b00: DataMisalignedM = 0; // lb, sb, lbu
2'b01: DataMisalignedM = IEUAdrM[0]; // lh, sh, lhu
2'b10: DataMisalignedM = IEUAdrM[1] | IEUAdrM[0]; // lw, sw, flw, fsw, lwu
2'b11: DataMisalignedM = |IEUAdrM[2:0]; // ld, sd, fld, fsd
endcase
// Determine if address is valid
assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[1];
assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[0];
assign LoadMisalignedFaultM = DataMisalignedM & MemRWMtoLRSC[1];
assign StoreMisalignedFaultM = DataMisalignedM & MemRWMtoLRSC[0];
// conditional
// 1. ram // controlled by `MEM_DTIM
@ -369,28 +299,19 @@ module lsu
// 3. wire pass-through
assign MemAdrE_RENAME = SelReplayCPURequest ? IEUAdrM[11:0] : MemAdrE[11:0];
dcache dcache(.clk(clk),
.reset(reset),
.StallWtoDCache(StallWtoDCache),
dcache dcache(.clk, .reset, .CPUBusy,
.MemRWM(MemRWMtoDCache),
.Funct3M(Funct3MtoDCache),
.Funct7M(Funct7M),
.FlushDCacheM,
.Funct7M, .FlushDCacheM,
.AtomicM(AtomicMtoDCache),
.MemAdrE(MemAdrE_RENAME),
.MemPAdrM(MemPAdrM),
.MemPAdrM,
.VAdr(IEUAdrM[11:0]), // this will be removed once the dcache hptw interlock is removed.
.WriteDataM(WriteDataM),
.ReadDataM(ReadDataM),
.DCacheStall(DCacheStall),
.WriteDataM, .ReadDataM, .DCacheStall,
.CommittedM(CommittedMfromDCache),
.DCacheMiss,
.DCacheAccess,
.ExceptionM(ExceptionM),
.IgnoreRequest,
.DCacheMiss, .DCacheAccess, .ExceptionM, .IgnoreRequest,
.PendingInterruptM(PendingInterruptMtoDCache),
.CacheableM(CacheableMtoDCache),
.MemAfterIWalkDone,
// AHB connection
.AHBPAdr(DCtoAHBPAdrM),

105
wally-pipelined/src/lsu/lsuArb.sv
View File

@ -1,105 +0,0 @@
///////////////////////////////////////////
// lsuArb.sv
//
// Written: Ross THompson and Kip Macsai-Goren
// Modified: kmacsaigoren@hmc.edu June 23, 2021
//
// Purpose: LSU arbiter between the CPU's demand request for data memory and
// the page table walker
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module lsuArb
(input logic clk,
// from page table walker
input logic SelPTW,
input logic HPTWRead,
input logic [`PA_BITS-1:0] TranslationPAdrE,
// from CPU
input logic [1:0] MemRWM,
input logic [2:0] Funct3M,
input logic [1:0] AtomicM,
input logic [`XLEN-1:0] IEUAdrM,
input logic [11:0] IEUAdrE,
input logic StallW,
input logic PendingInterruptM,
// to CPU
output logic DataMisalignedM,
output logic CommittedM,
//output logic LSUStall,
// to D Cache
output logic DisableTranslation,
output logic [1:0] MemRWMtoLRSC,
output logic [2:0] Funct3MtoDCache,
output logic [1:0] AtomicMtoDCache,
output logic [`PA_BITS-1:0] MemPAdrNoTranslate, // THis name is very bad. need a better name. This is the raw address from either the ieu or the hptw.
output logic [11:0] MemAdrE,
output logic StallWtoDCache,
output logic PendingInterruptMtoDCache,
// from D Cache
input logic CommittedMfromDCache,
input logic DataMisalignedMfromDCache,
input logic DCacheStall
);
logic [2:0] PTWSize;
logic [`PA_BITS-1:0] TranslationPAdrM;
logic [`XLEN+1:0] IEUAdrMExt;
// multiplex the outputs to LSU
assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
assign MemRWMtoLRSC = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
generate
assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
endgenerate
mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache);
// this is for the d cache SRAM.
flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdrE, TranslationPAdrM); // delay TranslationPAdrM by a cycle
assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
assign IEUAdrMExt = {2'b00, IEUAdrM};
assign MemPAdrNoTranslate = SelPTW ? TranslationPAdrM : IEUAdrMExt[`PA_BITS-1:0];
assign MemAdrE = SelPTW ? TranslationPAdrE[11:0] : IEUAdrE[11:0];
assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
// always block interrupts when using the hardware page table walker.
assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
// demux the inputs from LSU to walker or cpu's data port.
// works without the demux 7/18/21 dh. Suggest deleting these and removing fromDCache suffix
assign DataMisalignedM = /*SelPTW ? 1'b0 : */DataMisalignedMfromDCache;
// *** need to rename DcacheStall and Datastall.
// not clear at all. I think it should be LSUStall from the LSU,
// which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
//assign HPTWStall = SelPTW ? DCacheStall : 1'b1;
assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM;
//assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change.
endmodule

33
wally-pipelined/src/mmu/hptw.sv
View File

@ -5,7 +5,7 @@
// Modified: david_harris@hmc.edu 18 July 2021 cleanup and simplification
// kmacsaigoren@hmc.edu 1 June 2021
// implemented SV48 on top of SV39. This included, adding a level of the FSM for the extra page number segment
// adding support for terapage encoding, and for setting the TranslationPAdr using the new level,
// adding support for terapage encoding, and for setting the HPTWAdr using the new level,
// adding the internal SvMode signal
//
// Purpose: Page Table Walker
@ -35,18 +35,17 @@ module hptw
input logic clk, reset,
input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
input logic [`XLEN-1:0] PCF, IEUAdrM, // addresses to translate
input logic ITLBMissF, DTLBMissM, // TLB Miss
(* mark_debug = "true" *) input logic ITLBMissF, DTLBMissM, // TLB Miss
input logic [1:0] MemRWM, // 10 = read, 01 = write
input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU
input logic DCacheStall, // stall from LSU
input logic MemAfterIWalkDone,
input logic AnyCPUReqM,
output logic [`XLEN-1:0] PTE, // page table entry to TLBs
output logic [1:0] PageType, // page type to TLBs
output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
output logic HPTWStall,
output logic [`PA_BITS-1:0] TranslationPAdr,
(* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
output logic [`PA_BITS-1:0] HPTWAdr,
output logic HPTWRead, // HPTW requesting to read memory
output logic [2:0] HPTWSize, // 32 or 64 bit access.
output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
);
@ -54,7 +53,7 @@ module hptw
L1_ADR, L1_RD,
L2_ADR, L2_RD,
L3_ADR, L3_RD,
LEAF, LEAF_DELAY, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
LEAF, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
generate
if (`MEM_VIRTMEM) begin
@ -72,7 +71,7 @@ module hptw
logic [`SVMODE_BITS-1:0] SvMode;
logic [`XLEN-1:0] TranslationVAdr;
statetype WalkerState, NextWalkerState, InitialWalkerState;
(* mark_debug = "true" *) statetype WalkerState, NextWalkerState, InitialWalkerState;
// Extract bits from CSRs and inputs
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
@ -100,7 +99,6 @@ module hptw
// Enable and select signals based on states
assign StartWalk = (WalkerState == IDLE) & TLBMiss;
assign HPTWRead = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
assign HPTWStall = (WalkerState != IDLE) & (WalkerState != FAULT);
assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
@ -120,13 +118,14 @@ module hptw
default: NextPageType = PageType;
endcase
// TranslationPAdr muxing
// HPTWAdr muxing
if (`XLEN==32) begin // RV32
logic [9:0] VPN;
logic [`PPN_BITS-1:0] PPN;
assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state
assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN;
assign TranslationPAdr = {PPN, VPN, 2'b00};
assign HPTWAdr = {PPN, VPN, 2'b00};
assign HPTWSize = 3'b010;
end else begin // RV64
logic [8:0] VPN;
logic [`PPN_BITS-1:0] PPN;
@ -139,7 +138,8 @@ module hptw
endcase
assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) |
(SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN;
assign TranslationPAdr = {PPN, VPN, 3'b000};
assign HPTWAdr = {PPN, VPN, 3'b000};
assign HPTWSize = 3'b011;
end
// Initial state and misalignment for RV32/64
@ -198,10 +198,8 @@ module hptw
else NextWalkerState = LEAF;
// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
// else NextWalkerState = FAULT;
LEAF: if (DTLBWalk) NextWalkerState = IDLE; // updates TLB
else NextWalkerState = IDLE;
LEAF_DELAY: NextWalkerState = IDLE; // give time to allow address translation
FAULT: if (ITLBMissF & AnyCPUReqM & ~MemAfterIWalkDone) NextWalkerState = FAULT;
LEAF: NextWalkerState = IDLE; // updates TLB
FAULT: if (ITLBMissF & AnyCPUReqM) NextWalkerState = FAULT; /// **** BUG: Stays in fault 1 cycle longer than it should.
else NextWalkerState = IDLE;
default: begin
// synthesis translate_off
@ -213,7 +211,8 @@ module hptw
end else begin // No Virtual memory supported; tie HPTW outputs to 0
assign HPTWRead = 0;
assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0;
assign TranslationPAdr = 0;
assign HPTWAdr = 0;
assign HPTWSize = 3'b000;
end
endgenerate
endmodule

2
wally-pipelined/src/privileged/csrc.sv
View File

@ -92,7 +92,7 @@ module csrc #(parameter
generate
if (`ZICOUNTERS_SUPPORTED) begin
logic [63:0] CYCLE_REGW, INSTRET_REGW;
(* mark_debug = "true" *) logic [63:0] CYCLE_REGW, INSTRET_REGW;
logic [63:0] CYCLEPlusM, INSTRETPlusM;
logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
logic WriteCYCLEM, WriteINSTRETM;

2
wally-pipelined/src/privileged/privileged.sv
View File

@ -98,7 +98,7 @@ module privileged (
logic IllegalInstrFaultM, TrappedSRETM;
logic MTrapM, STrapM, UTrapM;
logic InterruptM;
(* mark_debug = "true" *) logic InterruptM;
logic STATUS_SPP, STATUS_TSR, STATUS_TW;
logic STATUS_MIE, STATUS_SIE;

6
wally-pipelined/testbench/testbench-linux.sv
View File

@ -283,8 +283,10 @@ module testbench();
`INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,3);
generate
genvar i;
/* -----\/----- EXCLUDED -----\/-----
`INIT_CHECKPOINT_GENBLK_ARRAY(PMP_BASE, PMPCFG, [7:0],`PMP_ENTRIES-1,0);
`INIT_CHECKPOINT_GENBLK_ARRAY(PMP_BASE, PMPADDR, [`XLEN-1:0],`PMP_ENTRIES-1,0);
-----/\----- EXCLUDED -----/\----- */
endgenerate
`INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]);
@ -449,7 +451,7 @@ module testbench();
force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
else \
release dut.hart.ieu.dp.ReadDataM; \
if(textM.substr(0,5) == "rrame") begin \
if(textM.substr(0,5) == "rdtime") begin \
//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \
end \
@ -547,7 +549,7 @@ module testbench();
#1;
// override on special conditions
if(~dut.hart.StallW) begin
if(textW.substr(0,5) == "rrame") begin
if(textW.substr(0,5) == "rdtime") begin
//$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW);
release dut.uncore.clint.clint.MTIME;
end