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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
David Harris 2021-01-28 00:22:11 -05:00
commit be1d1886a9
2 changed files with 12 additions and 12 deletions
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20
wally-pipelined/regression/wally-busybear.do
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@ -42,8 +42,8 @@ add wave /testbench_busybear/reset
add wave -divider add wave -divider
add wave -hex /testbench_busybear/PCtext add wave -hex /testbench_busybear/PCtext
add wave -hex /testbench_busybear/pcExpected add wave -hex /testbench_busybear/pcExpected
add wave -hex /testbench_busybear/dut/ieu/dp/PCF add wave -hex /testbench_busybear/dut/ifu/PCF
add wave -hex /testbench_busybear/dut/ieu/dp/InstrF add wave -hex /testbench_busybear/dut/ifu/InstrF
add wave /testbench_busybear/lastInstrF add wave /testbench_busybear/lastInstrF
add wave /testbench_busybear/speculative add wave /testbench_busybear/speculative
add wave /testbench_busybear/lastPC2 add wave /testbench_busybear/lastPC2
@ -87,27 +87,27 @@ add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[29]
add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[30] add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[30]
add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[31] add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[31]
add wave /testbench_busybear/InstrFName add wave /testbench_busybear/InstrFName
add wave -hex /testbench_busybear/dut/ieu/dp/PCD add wave -hex /testbench_busybear/dut/ifu/PCD
#add wave -hex /testbench_busybear/dut/ieu/dp/InstrD #add wave -hex /testbench_busybear/dut/ifu/InstrD
add wave /testbench_busybear/InstrDName add wave /testbench_busybear/InstrDName
#add wave -divider #add wave -divider
add wave -hex /testbench_busybear/dut/ieu/dp/PCE add wave -hex /testbench_busybear/dut/ifu/PCE
##add wave -hex /testbench_busybear/dut/ieu/dp/InstrE ##add wave -hex /testbench_busybear/dut/ifu/InstrE
add wave /testbench_busybear/InstrEName add wave /testbench_busybear/InstrEName
#add wave -hex /testbench_busybear/dut/ieu/dp/SrcAE #add wave -hex /testbench_busybear/dut/ieu/dp/SrcAE
#add wave -hex /testbench_busybear/dut/ieu/dp/SrcBE #add wave -hex /testbench_busybear/dut/ieu/dp/SrcBE
add wave -hex /testbench_busybear/dut/ieu/dp/ALUResultE add wave -hex /testbench_busybear/dut/ieu/dp/ALUResultE
#add wave /testbench_busybear/dut/ieu/dp/PCSrcE #add wave /testbench_busybear/dut/ieu/dp/PCSrcE
#add wave -divider #add wave -divider
add wave -hex /testbench_busybear/dut/ieu/dp/PCM add wave -hex /testbench_busybear/dut/ifu/PCM
##add wave -hex /testbench_busybear/dut/ieu/dp/InstrM ##add wave -hex /testbench_busybear/dut/ifu/InstrM
add wave /testbench_busybear/InstrMName add wave /testbench_busybear/InstrMName
#add wave /testbench_busybear/dut/dmem/dtim/memwrite #add wave /testbench_busybear/dut/dmem/dtim/memwrite
#add wave -hex /testbench_busybear/dut/dmem/AdrM #add wave -hex /testbench_busybear/dut/dmem/AdrM
#add wave -hex /testbench_busybear/dut/dmem/WriteDataM #add wave -hex /testbench_busybear/dut/dmem/WriteDataM
#add wave -divider #add wave -divider
add wave -hex /testbench_busybear/dut/ieu/dp/PCW add wave -hex /testbench_busybear/dut/ifu/PCW
##add wave -hex /testbench_busybear/dut/ieu/dp/InstrW ##add wave -hex /testbench_busybear/dut/ifu/InstrW
add wave /testbench_busybear/InstrWName add wave /testbench_busybear/InstrWName
#add wave /testbench_busybear/dut/ieu/dp/RegWriteW #add wave /testbench_busybear/dut/ieu/dp/RegWriteW
#add wave -hex /testbench_busybear/dut/ieu/dp/ResultW #add wave -hex /testbench_busybear/dut/ieu/dp/ResultW

4
wally-pipelined/testbench/testbench-busybear.sv
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@ -175,8 +175,8 @@ module testbench_busybear();
logic [31:0] InstrW; logic [31:0] InstrW;
instrNameDecTB dec(InstrF, InstrFName); instrNameDecTB dec(InstrF, InstrFName);
instrTrackerTB it(clk, reset, dut.ieu.dp.FlushE, instrTrackerTB it(clk, reset, dut.ieu.dp.FlushE,
dut.ieu.dp.InstrDecompD, dut.ieu.dp.InstrE, dut.ifu.InstrD, dut.ifu.InstrE,
dut.ieu.dp.InstrM, InstrW, dut.ifu.InstrM, InstrW,
InstrDName, InstrEName, InstrMName, InstrWName); InstrDName, InstrEName, InstrMName, InstrWName);
// generate clock to sequence tests // generate clock to sequence tests