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Optimized out second adder from IFU for PC+2

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This commit is contained in:
David Harris 2022-01-27 16:06:24 +00:00
parent 7f91170bab
commit bdd5796f3a
1 changed files with 45 additions and 41 deletions
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8
pipelined/src/ifu/ifu.sv
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@ -123,8 +123,10 @@ module ifu (
logic SelSpill, SpillSave;
logic [15:0] SpillDataLine0;
// *** PLACE ALL THIS IN A MODULE
// this exists only if there are compressed instructions.
assign PCFp2 = PCF + `XLEN'b10;
//assign PCFp2 = PCF + `XLEN'b10; **
assign PCFp2 = PCF[1] ? {PCPlusUpperF, 2'b00} : {PCF[`XLEN-1:2], 2'b10}; // recode as mux
assign PCNextFSpill = SelNextSpill ? PCFp2 : PCNextF;
assign PCFSpill = SelSpill ? PCFp2 : PCF;
@ -377,13 +379,15 @@ module ifu (
// pcadder
// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
assign PCPlusUpperF = PCF[`XLEN-1:2] + 1; // add 4 to PC
// choose PC+2 or PC+4
// choose PC+2 or PC+4 based on CompressedF, which arrives later.
// Speeds up critical path as compared to selecting adder input based on CompressedF
always_comb
if (CompressedF) // add 2
if (PCF[1]) PCPlus2or4F = {PCPlusUpperF, 2'b00};
else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4
// Decode stage pipeline register and logic
flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);