change ifndef to generate/if

wally-pipelined/config/busybear/wally-config.vh

@@ -86,6 +86,8 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
+// Busybear special CSR config to match OVPSim
+`define OVPSIM_CSR_CONFIG 1
 
 // Hardware configuration
 `define UART_PRESCALE 1

wally-pipelined/config/coremark/wally-config.vh

@@ -82,6 +82,8 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
+// Busybear special CSR config to match OVPSim
+`define OVPSIM_CSR_CONFIG 0
 
 // Hardware configuration
 `define UART_PRESCALE 1

wally-pipelined/config/coremark_bare/wally-config.vh

@@ -82,6 +82,8 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
+// Busybear special CSR config to match OVPSim
+`define OVPSIM_CSR_CONFIG 0
 
 // Hardware configuration
 `define UART_PRESCALE 1

wally-pipelined/config/rv32ic/wally-config.vh

@@ -81,6 +81,8 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
+// Busybear special CSR config to match OVPSim
+`define OVPSIM_CSR_CONFIG 0
 
 // Hardware configuration
 `define UART_PRESCALE 1

wally-pipelined/config/rv64ic/wally-config.vh

@@ -82,6 +82,8 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
+// Busybear special CSR config to match OVPSim
+`define OVPSIM_CSR_CONFIG 0
 
 // Hardware configuration
 `define UART_PRESCALE 1

wally-pipelined/config/rv64icfd/wally-config.vh

@@ -82,6 +82,8 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
+// Busybear special CSR config to match OVPSim
+`define OVPSIM_CSR_CONFIG 0
 
 // Hardware configuration
 `define UART_PRESCALE 1

wally-pipelined/src/privileged/csrm.sv

@@ -125,11 +125,12 @@ module csrm #(parameter
   flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); 
   flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW); 
   flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
-  `ifndef BUSYBEAR
-  flopenl #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], allones, MCOUNTEREN_REGW);
-  `else
-  flopenl #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, MCOUNTEREN_REGW);
-  `endif
+  generate
+    if (`OVPSIM_CSR_CONFIG)
+      flopenl #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, MCOUNTEREN_REGW);
+    else
+      flopenl #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], allones, MCOUNTEREN_REGW);
+  endgenerate
   flopenl #(32)   MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], allones, MCOUNTINHIBIT_REGW);
   flopenr #(`XLEN) PMPADDR0reg(clk, reset, WritePMPADDR0M, CSRWriteValM, PMPADDR0_REGW);  
   // PMPCFG registers are a pair of 64-bit in RV64 and four 32-bit in RV32

wally-pipelined/src/privileged/csrs.sv

@@ -82,11 +82,10 @@ module csrs #(parameter
       flopenl #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, zero, SCAUSE_REGW); 
       flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
       flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
-      `ifndef BUSYBEAR
-      flopenl #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], allones, SCOUNTEREN_REGW);
-      `else
-      flopenl #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, SCOUNTEREN_REGW);
-      `endif
+      if (`OVPSIM_CSR_CONFIG)
+        flopenl #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, SCOUNTEREN_REGW);
+      else
+        flopenl #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], allones, SCOUNTEREN_REGW);
       if (`N_SUPPORTED) begin
         logic WriteSEDELEGM, WriteSIDELEGM;
         assign WriteSEDELEGM = CSRSWriteM && (CSRAdrM == SEDELEG);