forked from Github_Repos/cvw
small bug fixes to 64 bit library
This commit is contained in:
Kip Macsai-Goren
parent
7412979b71
commit
ba7f976f92
@ -117,7 +117,7 @@ cause_ecall:
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cause_time_interrupt:
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// The following code works for both RV32 and RV64.
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// RV64 alone would be easier using double-word adds and stores
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li x28, 0x100 // Desired offset from the present time
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li x28, 0x30 // Desired offset from the present time
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la x29, 0x02004000 // MTIMECMP register in CLINT
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la x30, 0x0200BFF8 // MTIME register in CLINT
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lw x7, 0(x30) // low word of MTIME
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@ -158,9 +158,7 @@ end_trap_triggers:
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// Set up the exception Handler, keeping the original handler in x4.
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la x1, trap_handler_\MODE\()
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.if (\VECTORED\() == 1)
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ori x1, x1, 0x1 // set mode field of tvec to 1, forcing vectored interrupts
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.endif
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ori x1, x1, \VECTORED // set mode field of tvec to VECTORED, which will force vectored interrupts if it's 1.
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.if (\MODE\() == m)
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csrrw x4, \MODE\()tvec, x1 // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
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@ -172,6 +170,10 @@ end_trap_triggers:
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li a1, 0
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li a2, 0 // reset trap handler inputs to zero
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la x29, 0x02004000 // MTIMECMP register in CLINT
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li x30, 0xFFFFFFFF
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sd x30, 0(x29) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
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j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
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// ---------------------------------------------------------------------------------------------
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@ -214,17 +216,17 @@ trap_handler_\MODE\():
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// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
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// otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
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// No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
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j s_soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
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j soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
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j segfault_\MODE\() // 2: reserved
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j m_soft_interrupt_\MODE\() // 3: breakpoint
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j soft_interrupt_\MODE\() // 3: breakpoint
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j segfault_\MODE\() // 4: reserved
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j s_time_interrupt_\MODE\() // 5: load access fault
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j time_interrupt_\MODE\() // 5: load access fault
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j segfault_\MODE\() // 6: reserved
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j m_time_interrupt_\MODE\() // 7: store access fault
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j time_interrupt_\MODE\() // 7: store access fault
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j segfault_\MODE\() // 8: reserved
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j s_ext_interrupt_\MODE\() // 9: ecall from S-mode
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j ext_interrupt_\MODE\() // 9: ecall from S-mode
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j segfault_\MODE\() // 10: reserved
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j m_ext_interrupt_\MODE\() // 11: ecall from M-mode
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j ext_interrupt_\MODE\() // 11: ecall from M-mode
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// 12 through >=16 are reserved or designated for platform use
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trap_unvectored_\MODE\():
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@ -250,7 +252,6 @@ trap_unvectored_\MODE\():
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.else
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li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
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.endif
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and x5, x5, x1
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sd x5, 0(x16) // store masked out status bits to the output
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addi x6, x6, 8
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@ -265,7 +266,6 @@ trap_unvectored_\MODE\():
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and x5, x5, x1
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bnez x5, trapreturn_\MODE\() // return from interrupt
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// Other trap handling is specified in the vector Table
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csrr x1, \MODE\()cause
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slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
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la x5, exception_vector_table_\MODE\()
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add x5, x5, x1 // compute address of vector in Table
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@ -345,7 +345,7 @@ trapreturn_finished_\MODE\():
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csrw \MODE\()epc, x1 // update the epc with address of next instruction
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ld x5, -16(sp) // restore registers from stack before returning
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ld x1, -8(sp)
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csrw \MODE\()ip, 0x0 // clear interrupt pending register to indicate interrupt has been handled
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// *** this should be handled by indirectly clearing this bit csrw \MODE\()ip, 0x0 // clear interrupt pending register to indicate interrupt has been handled
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\MODE\()ret // return from trap
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ecallhandler_\MODE\():
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@ -376,7 +376,7 @@ ecallhandler_changetosupervisormode_\MODE\():
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ecallhandler_changetousermode_\MODE\():
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// Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret
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li x1, 0b1100000000000
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csrc mstatus, x1
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csrc \MODE\()status, x1
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j trapreturn_\MODE\()
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instrpagefault_\MODE\():
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@ -400,7 +400,7 @@ addr_misaligned_\MODE\():
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breakpt_\MODE\():
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j trapreturn_\MODE\()
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s_soft_interrupt_\MODE\(): // these labels are here to make sure the code compiles, but don't actually do anything yet
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soft_interrupt_\MODE\():
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li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table.
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sd x5, 0(x16)
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addi x6, x6, 8
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@ -409,30 +409,19 @@ s_soft_interrupt_\MODE\(): // these labels are here to make sure the code compil
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sw x0, 0(x28)
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j trap_unvectored_\MODE\()
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m_soft_interrupt_\MODE\():
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time_interrupt_\MODE\():
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li x5, 0x7EC
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sd x5, 0(x16)
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addi x6, x6, 8
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addi x16, x16, 8
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la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
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sw x0, 0(x28)
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la x29, 0x02004000 // MTIMECMP register in CLINT
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li x30, 0xFFFFFFFF
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sd x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
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j trap_unvectored_\MODE\()
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s_time_interrupt_\MODE\():
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li x5, 0x7EC
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sd x5, 0(x16)
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addi x6, x6, 8
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addi x16, x16, 8
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j trap_unvectored_\MODE\()
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m_time_interrupt_\MODE\():
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li x5, 0x7EC
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sd x5, 0(x16)
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addi x6, x6, 8
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addi x16, x16, 8
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j trap_unvectored_\MODE\()
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s_ext_interrupt_\MODE\():
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ext_interrupt_\MODE\():
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li x5, 0x7EC
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sd x5, 0(x16)
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addi x6, x6, 8
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@ -442,17 +431,6 @@ s_ext_interrupt_\MODE\():
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sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
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j trap_unvectored_\MODE\()
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m_ext_interrupt_\MODE\():
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li x5, 0x7EC
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sd x5, 0(x16)
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addi x6, x6, 8
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addi x16, x16, 8
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li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
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sw x0, 8(x28) // disable the first pin as an output
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sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
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j trap_unvectored_\MODE\()
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// Table of trap behavior
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// lists what to do on each exception (not interrupts)
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// unexpected exceptions should cause segfaults for easy detection
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@ -720,87 +698,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
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addi x16, x16, 8
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.endm
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// // The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines
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// // This effectively includes everything that isn't to do with page faults (virtual memory)
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// .macro CAUSE_INSTR_ADDR_MISALIGNED
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// // cause a misaligned address trap
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// auipc x28, 0 // get current PC, which is aligned
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// addi x28, x28, 0x1 // add 1 to pc to create misaligned address
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// jalr x28 // cause instruction address midaligned trap
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// .endm
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// .macro CAUSE_INSTR_ACCESS
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// la x28, 0x0 // address zero is an address with no memory
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// jalr x28 // cause instruction access trap
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// .endm
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// .macro CAUSE_ILLEGAL_INSTR
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// .word 0x00000000 // a 32 bit zros is an illegal instruction
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// .endm
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// .macro CAUSE_BREAKPNT // ****
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// ebreak
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// .endm
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// .macro CAUSE_LOAD_ADDR_MISALIGNED
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// auipc x28, 0 // get current PC, which is aligned
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// addi x28, x28, 1
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// lw x29, 0(x28) // load from a misaligned address
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// .endm
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// .macro CAUSE_LOAD_ACC
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// la x28, 0 // 0 is an address with no memory
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// lw x29, 0(x28) // load from unimplemented address
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// .endm
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// .macro CAUSE_STORE_ADDR_MISALIGNED
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// auipc x28, 0 // get current PC, which is aligned
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// addi x28, x28, 1
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// sw x29, 0(x28) // store to a misaligned address
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// .endm
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// .macro CAUSE_STORE_ACC
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// la x28, 0 // 0 is an address with no memory
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// sw x29, 0(x28) // store to unimplemented address
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// .endm
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// .macro CAUSE_ECALL
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// // *** ASSUMES you have already gone to the mode you need to call this from.
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// ecall
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// .endm
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// .macro CAUSE_TIME_INTERRUPT
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// // The following code works for both RV32 and RV64.
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// // RV64 alone would be easier using double-word adds and stores
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// li x28, 0x100 // Desired offset from the present time
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// la x29, 0x02004000 // MTIMECMP register in CLINT
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// la x30, 0x0200BFF8 // MTIME register in CLINT
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// lw x7, 0(x30) // low word of MTIME
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// lw x31, 4(x30) // high word of MTIME
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// add x28, x7, x28 // add desired offset to the current time
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// bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound)
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// addi x31, x31, 1 // if wrap, increment most significant word
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// sw x31,4(x29) // store into most significant word of MTIMECMP
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// nowrap:
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// sw x28, 0(x29) // store into least significant word of MTIMECMP
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// loop: j loop // wait until interrupt occurs
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// .endm
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// .macro CAUSE_SOFT_INTERRUPT
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// la x28, 0x02000000 // MSIP register in CLINT
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// li x29, 1 // 1 in the lsb
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// sw x29, 0(x28) // Write MSIP bit
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// .endm
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// .macro CAUSE_EXT_INTERRUPT
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// li x28, 0x10060000 // load base GPIO memory location
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// li x29, 0x1
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// sw x29, 8(x28) // enable the first pin as an output
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// sw x29, 28(x28) // set first pin to high interrupt enable
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// sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
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// .endm
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.macro END_TESTS
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// invokes one final ecall to return to machine mode then terminates this program, so the output is
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// 0x8: termination called from U mode
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