forked from Github_Repos/cvw
		
	Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s).
Increased CPU clock speed from 30 Mhz to 35 Mhz.
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				@ -15,12 +15,12 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
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			CONFIG.No_Controller {1} \
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			CONFIG.Phy_Only {Complete_Memory_Controller} \
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			CONFIG.C0.DDR4_PhyClockRatio {4:1} \
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			CONFIG.C0.DDR4_TimePeriod {1200} \
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			CONFIG.C0.DDR4_TimePeriod {833} \
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			CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \
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			CONFIG.C0.DDR4_BurstLength {8} \
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			CONFIG.C0.DDR4_BurstType {Sequential} \
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			CONFIG.C0.DDR4_CasLatency {13} \
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			CONFIG.C0.DDR4_CasWriteLatency {10} \
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			CONFIG.C0.DDR4_CasLatency {16} \
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			CONFIG.C0.DDR4_CasWriteLatency {12} \
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			CONFIG.C0.DDR4_Slot {Single} \
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			CONFIG.C0.DDR4_MemoryVoltage {1.2V} \
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			CONFIG.C0.DDR4_DataWidth {64} \
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@ -36,14 +36,11 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
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			CONFIG.C0.DDR4_AxiIDWidth {4} \
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			CONFIG.C0.DDR4_AxiAddressWidth {31} \
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			CONFIG.C0.DDR4_AxiNarrowBurst {false} \
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			CONFIG.C0.DDR4_CLKFBOUT_MULT {5} \
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			CONFIG.C0.DDR4_DIVCLK_DIVIDE {1} \
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			CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
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			CONFIG.Reference_Clock {Differential} \
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			CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
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			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {30} \
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			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {35} \
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			CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
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			CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
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			CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
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			CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
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			CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \
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			CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \
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@ -21,8 +21,8 @@
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	cpus {
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		#address-cells = <0x01>;
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		#size-cells = <0x00>;
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		clock-frequency = <0x1C9C380>;
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		timebase-frequency = <0x1C9C380>;
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		clock-frequency = <0x211D0D0>;
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		timebase-frequency = <0x211D0D0>;
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		cpu@0 {
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			phandle = <0x01>;
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@ -51,7 +51,7 @@
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		uart@10000000 {
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			interrupts = <0x0a>;
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			interrupt-parent = <0x03>;
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			clock-frequency = <0x1C9C380>;
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			clock-frequency = <0x211D0D0>;
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			reg = <0x00 0x10000000 0x00 0x100>;
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			compatible = "ns16550a";
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		};
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