forked from Github_Repos/cvw
Revert "broke it again but this time it doesn't compile due to a missing semicolon on Rs1D."
This reverts commit f970cc3ea9
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fixed it
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f970cc3ea9
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b7d036f3d0
@ -88,7 +88,7 @@ module datapath (
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logic [`XLEN-1:0] IFResultW;
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// Decode stage
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assign Rs1D = InstrD[19:15]
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assign Rs1D = InstrD[19:15];
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assign Rs2D = InstrD[24:20];
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assign RdD = InstrD[11:7];
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regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);
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