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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2022-03-31 15:50:04 -05:00
commit b5cdf035fc
2 changed files with 2 additions and 6 deletions
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2
pipelined/src/fma/fma.do
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@ -8,7 +8,7 @@ onbreak {resume}
# create library # create library
vlib worklib vlib worklib
vlog -lint -work worklib fma16.v testbench.v vlog -lint -sv -work worklib fma16.v testbench.v
vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt
vsim -lib worklib testbenchopt vsim -lib worklib testbenchopt

6
pipelined/src/uncore/plic.sv
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@ -176,11 +176,7 @@ module plic (
end end
// pending interrupt requests // pending interrupt requests
assign nextIntPending = assign nextIntPending = (intPending | requests) & ~intInProgress;
(intPending | // existing pending requests
(requests & ~intInProgress)) & // assert new requests (if they aren't already being serviced)
~({`N{((entry == 24'h200004) & memread)}} << (intClaim[0]-1)) & // deassert requests that just completed
~({`N{((entry == 24'h201004) & memread)}} << (intClaim[1]-1));
flopr #(`N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending); flopr #(`N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
// context-dependent signals // context-dependent signals