Introduce bugs for lab 3

pipelined/src/ieu/alu.sv

@@ -67,7 +67,7 @@ module alu #(parameter WIDTH=32) (
  
   // SLT
   assign SLT = {{(WIDTH-1){1'b0}}, LT};
-  assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
+  assign SLTU = {{(WIDTH-1){1'b0}}, LT};
  
   // Select appropriate ALU Result
   assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0

pipelined/src/ieu/controller.sv

@@ -98,7 +98,7 @@ module controller(
   logic       InstrValidD, InstrValidE;
   logic       PrivilegedD, PrivilegedE;
   logic       InvalidateICacheE, FlushDCacheE;
-  logic [`CTRLW-1:0] ControlsD;
+  logic       ControlsD;
   logic        SubArithD;
   logic        subD, sraD, sltD, sltuD;
   logic        BranchTakenE;

pipelined/src/ieu/datapath.sv

@@ -104,7 +104,7 @@ module datapath (
   flopenrc #(`XLEN) RD2EReg(clk, reset, FlushE, ~StallE, R2D, R2E);
   flopenrc #(`XLEN) ExtImmEReg(clk, reset, FlushE, ~StallE, ExtImmD, ExtImmE);
   flopenrc #(5)     Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
-  flopenrc #(5)     Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
+  flopenrc #(5)     Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs1E);
   flopenrc #(5)     RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
 	
   mux3  #(`XLEN)  faemux(R1E, WriteDataW, ResultM, ForwardAE, ForwardedSrcAE);

pipelined/testbench/testbench.sv

@@ -296,7 +296,7 @@ logic [3:0] dummy;
             ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
             ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
             $display("Read memfile %s", memfilename);
-            reset_ext = 1; # 47; reset_ext = 0;
+            reset_ext = 1; # 47; //reset_ext = 0;
         end
       end
     end // always @ (negedge clk)