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modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations)

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bbracker 2021-09-04 19:49:26 -04:00
parent c463f177e9
commit b3bc3cf6d0
1 changed files with 322 additions and 325 deletions
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69
wally-pipelined/testbench/testbench-linux.sv
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@ -30,8 +30,7 @@
module testbench(); module testbench();
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3080000; // # of instructions at which to turn on waves in graphical sim parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*6779000; // # of instructions at which to turn on waves in graphical sim
parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
string ProgramAddrMapFile, ProgramLabelMapFile; string ProgramAddrMapFile, ProgramLabelMapFile;
@ -72,9 +71,9 @@ module testbench();
// Signal Declarations // Signal Declarations
// ------------------- // -------------------
// Testbench Core // Testbench Core
integer instrs;
integer warningCount = 0; integer warningCount = 0;
// PC, Instr Checking integer errorCount = 0;
// P, Instr Checking
logic [`XLEN-1:0] PCW; logic [`XLEN-1:0] PCW;
integer data_file_all; integer data_file_all;
@ -137,12 +136,16 @@ module testbench();
// Error Macro // Error Macro
// ----------- // -----------
`define ERROR \ `define ERROR \
$display("processed %0d instructions with %0d warnings", instrs, warningCount); \ errorCount +=1; \
$display("processed %0d instructions with %0d warnings", InstrCountW, warningCount); \
$stop; $stop;
initial begin initial begin
data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
InstrCountW = '0; InstrCountW = '0;
force dut.hart.priv.SwIntM = 0;
force dut.hart.priv.TimerIntM = 0;
force dut.hart.priv.ExtIntM = 0;
end end
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
@ -160,7 +163,7 @@ module testbench();
flopenrc #(`XLEN) PCWReg(clk, reset, dut.hart.FlushW, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW); flopenrc #(`XLEN) PCWReg(clk, reset, dut.hart.FlushW, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
flopenr #(1) TrapWReg(clk, reset, ~dut.hart.StallW, dut.hart.hzu.TrapM, TrapW); flopenr #(1) TrapWReg(clk, reset, ~dut.hart.StallW, dut.hart.hzu.TrapM, TrapW);
// because qemu does not match exactly to wally it is necessary to read the the // Because qemu does not match exactly to wally it is necessary to read the the
// trace in the memory stage and detect if anything in wally must be overwritten. // trace in the memory stage and detect if anything in wally must be overwritten.
// This includes mtimer, interrupts, and various bits in mstatus and xtval. // This includes mtimer, interrupts, and various bits in mstatus and xtval.
@ -242,7 +245,7 @@ module testbench();
if(ExpectedCSRArrayM[NumCSRM].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRM][`XLEN-1] == 1'b1)) begin if(ExpectedCSRArrayM[NumCSRM].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRM][`XLEN-1] == 1'b1)) begin
//what type? //what type?
ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C; ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C;
$display("%t: CSR = %s. Forcing interrupt of cause = %x", $time, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]); $display("%tns, %d instrs: CSR = %s. Forcing interrupt of cause = %x", $time, InstrCountW, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]);
if(ExpectedIntType == 0) begin if(ExpectedIntType == 0) begin
force dut.hart.priv.SwIntM = 1'b1; force dut.hart.priv.SwIntM = 1'b1;
@ -262,11 +265,11 @@ module testbench();
end end
// override on special conditions // override on special conditions
if (ExpectedMemAdrM == 'h10000005) begin if (ExpectedMemAdrM == 'h10000005) begin
//$display("%t: Overwriting read data from CLINT.", $time); //$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW);
force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM;
end end
if(textM.substr(0,5) == "rdtime") begin if(textM.substr(0,5) == "rdtime") begin
$display("%t: Overwrite read value of CSR on read of MTIME in memory stage.", $time); $display("%tns, %d instrs: Overwrite read value of CSR on read of MTIME in memory stage.", $time, InstrCountW);
force dut.hart.priv.csr.CSRReadValM = ExpectedRegValueM; force dut.hart.priv.csr.CSRReadValM = ExpectedRegValueM;
//dut.hart.ieu.dp.regf.wd3 //dut.hart.ieu.dp.regf.wd3
end end
@ -325,25 +328,35 @@ module testbench();
if(~dut.hart.StallW) begin if(~dut.hart.StallW) begin
if(textM.substr(0,5) == "rdtime") begin if(textM.substr(0,5) == "rdtime") begin
$display("%t:Releasing force of CSRReadValM.", $time); $display("%tns, %d instrs: Releasing force of CSRReadValM.", $time, InstrCountW);
release dut.hart.priv.csr.CSRReadValM; release dut.hart.priv.csr.CSRReadValM;
//release dut.hart.ieu.dp.regf.wd3; //release dut.hart.ieu.dp.regf.wd3;
end end
if (ExpectedMemAdrM == 'h10000005) begin if (ExpectedMemAdrM == 'h10000005) begin
//$display("%t: releasing force of ReadDataM.", $time); //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW);
release dut.hart.ieu.dp.ReadDataM; release dut.hart.ieu.dp.ReadDataM;
end end
// remove forces on interrupts // force interrupts to 0
for(NumCSRMIndex = 0; NumCSRMIndex < NumCSRM; NumCSRMIndex++) begin for(NumCSRMIndex = 0; NumCSRMIndex < NumCSRM; NumCSRMIndex++) begin
if(ExpectedCSRArrayM[NumCSRMIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRMIndex][`XLEN-1] == 1'b1)) begin if(ExpectedCSRArrayM[NumCSRMIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRMIndex][`XLEN-1] == 1'b1)) begin
//what type? //what type?
$display("%t: Releasing all forces on interrupts", $time); ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C;
$display("%tns, %d instrs: CSR = %s. Forcing interrupt of cause = %x back to 0", $time, InstrCountW, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]);
release dut.hart.priv.SwIntM; if(ExpectedIntType == 0) begin
release dut.hart.priv.TimerIntM; force dut.hart.priv.SwIntM = 1'b0;
release dut.hart.priv.ExtIntM; $display("Force SwIntM");
end
else if(ExpectedIntType == 4) begin
force dut.hart.priv.TimerIntM = 1'b0;
$display("Force TimeIntM");
end
else if(ExpectedIntType == 8) begin
force dut.hart.priv.ExtIntM = 1'b0;
$display("Force ExtIntM");
end
end end
end end
end end
@ -355,6 +368,8 @@ module testbench();
// always check PC, instruction bits // always check PC, instruction bits
if (checkInstrW) begin if (checkInstrW) begin
InstrCountW += 1; InstrCountW += 1;
// turn on waves at certain point
if (InstrCountW == waveOnICount) $stop;
// check PCW // check PCW
fault = 0; fault = 0;
if(PCW != ExpectedPCW) begin if(PCW != ExpectedPCW) begin
@ -426,7 +441,7 @@ module testbench();
// check csr // check csr
//$display("%t, about to check csr, NumCSRW = %d", $time, NumCSRW); //$display("%t, about to check csr, NumCSRW = %d", $time, NumCSRW);
for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
if(`DEBUG_TRACE > 0) begin if(`DEBUG_TRACE > 0) begin
$display("%t, NumCSRPostWIndex = %d, Expected CSR: %s = %016x", $time, NumCSRPostWIndex, ExpectedCSRArrayW[NumCSRPostWIndex], ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("%t, NumCSRPostWIndex = %d, Expected CSR: %s = %016x", $time, NumCSRPostWIndex, ExpectedCSRArrayW[NumCSRPostWIndex], ExpectedCSRArrayValueW[NumCSRPostWIndex]);
end end
@ -504,7 +519,6 @@ module testbench();
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
"mtval": begin "mtval": begin
if(`DEBUG_TRACE > 0) begin if(`DEBUG_TRACE > 0) begin
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
@ -514,7 +528,6 @@ module testbench();
if(!`DontHaltOnCSRMisMatch) fault = 1; if(!`DontHaltOnCSRMisMatch) fault = 1;
end end
end end
"sepc": begin "sepc": begin
if(`DEBUG_TRACE > 0) begin if(`DEBUG_TRACE > 0) begin
$display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.SEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]); $display("CSR: %s = %016x, expected = %016x", ExpectedCSRArrayW[NumCSRPostWIndex], dut.hart.priv.csr.genblk1.csrs.SEPC_REGW, ExpectedCSRArrayValueW[NumCSRPostWIndex]);
@ -552,23 +565,8 @@ module testbench();
end end
end end
endcase // case (ExpectedCSRArrayW[NumCSRPostWIndex]) endcase // case (ExpectedCSRArrayW[NumCSRPostWIndex])
/* -----\/----- EXCLUDED -----\/-----
if(CurrentInterruptForce) begin
CurrentInterruptForce = 1'b0;
// remove forces on interrupts
$display("%t: Releasing all forces on interrupts", $time);
release dut.hart.priv.SwIntM;
release dut.hart.priv.TimerIntM;
release dut.hart.priv.ExtIntM;
end
-----/\----- EXCLUDED -----/\----- */
end // for (NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) end // for (NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++)
if (fault == 1) begin if (fault == 1) begin `ERROR end
`ERROR
end
end // if (checkInstrW) end // if (checkInstrW)
end // always @ (negedge clk) end // always @ (negedge clk)
@ -589,7 +587,6 @@ module testbench();
// -------------- // --------------
initial initial
begin begin
instrs = 0;
reset <= 1; # 22; reset <= 0; reset <= 1; # 22; reset <= 0;
end end
// initial loading of memories // initial loading of memories