Stripped write capaibilty out of rom_ahb

pipelined/src/uncore/rom_ahb.sv

@@ -32,45 +32,23 @@
 
 module rom_ahb #(parameter BASE=0, RANGE = 65535) (
   input  logic             HCLK, HRESETn, 
-  input  logic             HSELRam,
+  input  logic             HSELRom,
   input  logic [31:0]      HADDR,
-  input  logic             HWRITE,
   input  logic             HREADY,
   input  logic [1:0]       HTRANS,
-  input  logic [`XLEN-1:0] HWDATA,
-  input  logic [`XLEN/8-1:0] HWSTRB,
-  output logic [`XLEN-1:0] HREADRam,
-  output logic             HRESPRam, HREADYRam
+  output logic [`XLEN-1:0] HREADRom,
+  output logic             HRESPRom, HREADYRom
 );
 
   localparam ADDR_WIDTH = $clog2(RANGE/8);
   localparam OFFSET = $clog2(`XLEN/8);   
  
-  logic [`XLEN/8-1:0] 		  ByteMask;
-  logic [31:0]        HADDRD, RamAddr;
-  logic				  initTrans;
-  logic				  memwrite, memwriteD, memread;
-  logic         nextHREADYRam;
+  // Never stalls
+  assign HREADYRom = 1'b1;
+  assign HRESPRom = 0; // OK
 
-  // a new AHB transactions starts when HTRANS requests a transaction, 
-  // the peripheral is selected, and the previous transaction is completing
-  assign initTrans = HREADY & HSELRam & HTRANS[1]; 
-  assign memwrite = initTrans & HWRITE;  
-  assign memread = initTrans & ~HWRITE;
- 
-  flopenr #(1) memwritereg(HCLK, ~HRESETn, HREADY, memwrite, memwriteD); 
-  flopenr #(32)   haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD);
-
-  // Stall on a read after a write because the RAM can't take both adddresses on the same cycle
-  assign nextHREADYRam = ~(memwriteD & memread);
-  flopr #(1) readyreg(HCLK, ~HRESETn, nextHREADYRam, HREADYRam);
-  assign HRESPRam = 0; // OK
-
-  // On writes or during a wait state, use address delayed by one cycle to sync RamAddr with HWDATA or hold stalled address
-  mux2 #(32) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
-
-  // single-ported RAM
-  bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH)
-    memory(.clk(HCLK), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA));  
+  // single-ported ROM
+  brom1p1r #(ADDR_WIDTH, `XLEN)
+    memory(.clk(HCLK), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));  
 endmodule
   

pipelined/src/uncore/uncore.sv

@@ -120,10 +120,9 @@ module uncore (
     rom_ahb #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE))
     bootrom(
       .HCLK, .HRESETn, 
-      .HSELRam(HSELBootRom), .HADDR,
-      .HWRITE, .HREADY, .HTRANS, 
-      .HWDATA, .HWSTRB,
-      .HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom));
+      .HSELRom(HSELBootRom), .HADDR,
+      .HREADY, .HTRANS, 
+      .HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom));
   end
 
   // memory-mapped I/O peripherals

pipelined/testbench/testbench-linux.sv

@@ -421,9 +421,9 @@ module testbench;
     ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"};
     // initialize bootrom
     memFile = $fopen({testvectorDir,"bootmem.bin"}, "rb");
-    readResult = $fread(dut.uncore.bootrom.bootrom.memory.RAM,memFile);
+    readResult = $fread(dut.uncore.bootrom.bootrom.memory.ROM,memFile);
     $fclose(memFile);
-    // initialize RAM
+    // initialize RAM and ROM
     if (CHECKPOINT==0) 
       memFile = $fopen({testvectorDir,"ram.bin"}, "rb");
     else