Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

wally-pipelined/src/lsu/lsu.sv

@@ -217,7 +217,7 @@ module lsu (
 
   
     
-  mmu #(.TLB_ENTRIES(`DTLB_ENTRY_BITS), .IMMU(0))
+  mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
   dmmu(.TLBAccessType(MemRWMtoLSU),
        .VirtualAddress(MemAdrMtoLSU),
        .Size(Funct3MtoLSU[1:0]),

wally-pipelined/src/mmu/tlb.sv

@@ -95,7 +95,7 @@ module tlb #(parameter TLB_ENTRIES = 8,
   logic [`SVMODE_BITS-1:0] SvMode;
   logic  [1:0]       EffectivePrivilegeMode; // privilege mode, possibly modified by MPRV
 
-  logic [TLB_ENTRIES-1:0] ReadLines, WriteLines, WriteEnables, Global; // used as the one-hot encoding of WriteIndex
+  logic [TLB_ENTRIES-1:0] ReadLines, WriteLines, WriteEnables, PTE_G; // used as the one-hot encoding of WriteIndex
 
   // Sections of the virtual and physical addresses
   logic [`VPN_BITS-1:0] VirtualPageNumber;
@@ -107,7 +107,7 @@ module tlb #(parameter TLB_ENTRIES = 8,
   logic [7:0]           PTEAccessBits;
   logic [11:0]          PageOffset;
 
-  logic PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits
+  logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits
   logic [1:0]            HitPageType;
   logic                  CAMHit;
   logic [`ASID_BITS-1:0] ASID;
@@ -153,6 +153,7 @@ module tlb #(parameter TLB_ENTRIES = 8,
   tlbphysicalpagemask PageMask(VirtualPageNumber, PhysicalPageNumber, HitPageType, PhysicalPageNumberMixed);
 
   // unswizzle useful PTE bits
+  assign {PTE_D, PTE_A} = PTEAccessBits[7:6];
   assign {PTE_U, PTE_X, PTE_W, PTE_R} = PTEAccessBits[4:1];
  
   // Check whether the access is allowed, page faulting if not.

wally-pipelined/src/mmu/tlbcam.sv

@@ -36,7 +36,7 @@ module tlbcam #(parameter TLB_ENTRIES = 8,
   input logic [1:0]               PageTypeWriteVal,
   input logic                     TLBFlush,
   input logic [TLB_ENTRIES-1:0]   WriteEnables,
-  input logic [TLB_ENTRIES-1:0]   Global
+  input logic [TLB_ENTRIES-1:0]   PTE_G,
   input logic [`ASID_BITS-1:0]    ASID,
   output logic [TLB_ENTRIES-1:0]  ReadLines,
   output logic [1:0]              HitPageType,

wally-pipelined/src/mmu/tlbcamline.sv

@@ -34,7 +34,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
   input  logic [`VPN_BITS-1:0]  VirtualPageNumber, // The requested page number to compare against the key
   input  logic [`ASID_BITS-1:0] ASID,
   input  logic                  WriteEnable,  // Write a new entry to this line
-  input  logic                  Global,
+  input  logic                  PTE_G,
   input  logic [1:0]            PageTypeWriteVal,
   input  logic                  TLBFlush,   // Flush this line (set valid to 0)
   output logic [1:0]            PageTypeRead,  // *** should this be the stored version or the always updated one?
@@ -57,7 +57,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
   logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1;
   logic MatchASID, Match0, Match1;
 
-  assign MatchASID = (ASID == Key_ASID) | Global; 
+  assign MatchASID = (ASID == Key_ASID) | PTE_G; 
 
   generate
     if (`XLEN == 32) begin

wally-pipelined/src/mmu/tlbram.sv

@@ -33,14 +33,14 @@ module tlbram #(parameter TLB_ENTRIES = 8) (
   input logic [TLB_ENTRIES-1:0]     ReadLines, WriteEnables,
   output logic [`PPN_BITS-1:0]      PhysicalPageNumber,
   output logic [7:0]                PTEAccessBits,
-  output logic [TLB_ENTRIES-1:0]    Global
+  output logic [TLB_ENTRIES-1:0]    PTE_G
 );
 
   logic [`XLEN-1:0] RamRead[TLB_ENTRIES-1:0];
   logic [`XLEN-1:0] PageTableEntry;
 
   // Generate a flop for every entry in the RAM
-  tlbramline #(`XLEN) tlblineram[TLB_ENTRIES-1:0](clk, reset, ReadLines, WriteEnables, PTEWriteVal, RamRead);
+  tlbramline #(`XLEN) tlblineram[TLB_ENTRIES-1:0](clk, reset, ReadLines, WriteEnables, PTEWriteVal, RamRead, PTE_G);
   
   assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE
   assign PTEAccessBits = PageTableEntry[7:0];

wally-pipelined/src/mmu/tlbramline.sv

@@ -29,10 +29,12 @@ module tlbramline #(parameter WIDTH)
   (input  logic             clk, reset,
    input  logic             re, we,
    input  logic [WIDTH-1:0] d,
-   output logic [WIDTH-1:0] q);
+   output logic [WIDTH-1:0] q,
+   output logic             PTE_G);
 
    logic [WIDTH-1:0] line;
 
    flopenr #(`XLEN) pteflop(clk, reset, we, d, line);
    assign q = re ? line : 0;
+   assign PTE_G = line[5]; // send global bit to CAM as part of ASID matching
 endmodule