forked from Github_Repos/cvw
		
	Oups. My hack for DivE interrupt prevention was wrong.
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				@ -71,7 +71,7 @@ module trap (
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  assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) | ((PrivilegeModeW == `S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
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  assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
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  assign PendingInterruptM = (|PendingIntsM) & InstrValidM;  
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  assign InterruptM = PendingInterruptM & (~CommittedM | ~DivE);  // *** RT. temporary hack to prevent integer division from having an interrupt during divide.
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  assign InterruptM = PendingInterruptM & ~(CommittedM | DivE);  // *** RT. temporary hack to prevent integer division from having an interrupt during divide.
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  // ideally this should be disabled for all but the first cycle. However I'm not familar with the internals of the integer divider.  This should (could) be an issue for
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  // floating point and integer multiply.
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  //assign ExceptionM = TrapM;
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