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Replaced FPU data replicaiton on WriteData bus with 0 extention.

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This commit is contained in:
Ross Thompson 2022-08-23 10:46:03 -05:00
parent b9fadc11c3
commit b0606a1699
1 changed files with 1 additions and 14 deletions
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15
pipelined/src/fpu/fpu.sv
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@ -59,9 +59,6 @@ module fpu (
// single stored in a double: | 32 1s | single precision value |
// - sets the underflow after rounding
// LSU interface
logic [`FLEN-1:0] FWriteDataE;
// control signals
logic FRegWriteW; // FP register write enable
logic [2:0] FrmM; // FP rounding mode
@ -291,17 +288,7 @@ module fpu (
// - FP uses NaN-blocking format
// - if there are any unsused bits the most significant bits are filled with 1s
if(`FPSIZES == 1) assign FWriteDataE = YE;
else if(`FPSIZES == 2) assign FWriteDataE = FmtE ? YE : {`FLEN/`LEN1{YE[`LEN1-1:0]}};
else
always_comb
case(FmtE)
`Q_FMT: FWriteDataE = YE;
`D_FMT: FWriteDataE = {`FLEN/`D_LEN{YE[`D_LEN-1:0]}};
`S_FMT: FWriteDataE = {`FLEN/`S_LEN{YE[`S_LEN-1:0]}};
`H_FMT: FWriteDataE = {`FLEN/`H_LEN{YE[`H_LEN-1:0]}};
endcase
flopenrc #(`FLEN) FWriteDataMReg (clk, reset, FlushM, ~StallM, FWriteDataE, FWriteDataM);
flopenrc #(`FLEN) FWriteDataMReg (clk, reset, FlushM, ~StallM, YE, FWriteDataM);
// NaN Block SrcA
generate