forked from Github_Repos/cvw
Added integer division in srt, parametrized everything to work with integers and floating points, parametrized testbench.
This commit is contained in:
cturek
parent
8c84d5fdc7
commit
afdfe770fc
@ -17,7 +17,7 @@ if [file exists work] {
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}
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vlib work
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vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv
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vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/generic/lzc.sv
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vopt +acc work.testbench -o workopt
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vsim workopt
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@ -30,7 +30,11 @@
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`include "wally-config.vh"
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module srt #(parameter Nf=52) (
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`define DIVLEN ((`NF<(`XLEN+1)) ? (`XLEN + 1) : `NF)
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`define EXTRAFRACBITS ((`NF<(`XLEN+1)) ? (`XLEN - `NF + 1) : 0)
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`define EXTRAINTBITS ((`NF<(`XLEN+1)) ? 0 : (`NF - `XLEN))
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module srt (
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input logic clk,
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input logic Start,
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input logic Stall, // *** multiple pipe stages
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@ -39,7 +43,7 @@ module srt #(parameter Nf=52) (
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// later add exponents, signs, special cases
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input logic XSign, YSign,
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input logic [`NE-1:0] XExp, YExp,
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input logic [Nf-1:0] SrcXFrac, SrcYFrac,
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input logic [`NF-1:0] SrcXFrac, SrcYFrac,
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input logic [`XLEN-1:0] SrcA, SrcB,
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input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
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input logic W64, // 32-bit ints on XLEN=64
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@ -47,7 +51,7 @@ module srt #(parameter Nf=52) (
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input logic Int, // Choose integer inputs
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input logic Sqrt, // perform square root, not divide
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output logic rsign,
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output logic [Nf-1:0] Quot, Rem, QuotOTFC, // *** later handle integers
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output logic [`DIVLEN-1:0] Quot, Rem, QuotOTFC, // *** later handle integers
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output logic [`NE-1:0] rExp,
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output logic [3:0] Flags
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);
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@ -55,38 +59,40 @@ module srt #(parameter Nf=52) (
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logic qp, qz, qm; // quotient is +1, 0, or -1
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logic [`NE-1:0] calcExp;
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logic calcSign;
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logic [Nf-1:0] X, Dpreproc;
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logic [Nf+3:0] WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel;
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logic [Nf+2:0] rp, rm;
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logic [`DIVLEN-1:0] X, Dpreproc;
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logic [`DIVLEN+3:0] WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel;
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logic [`DIVLEN+2:0] rp, rm;
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logic [$clog2(`XLEN+1)-1:0] intExp;
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logic intSign;
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srtpreproc #(Nf) preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc);
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srtpreproc preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc, intExp, intSign);
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// Top Muxes and Registers
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// When start is asserted, the inputs are loaded into the divider.
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// Otherwise, the divisor is retained and the partial remainder
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// is fed back for the next iteration.
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mux2 #(Nf+4) wsmux({WSA[54:0], 1'b0}, {4'b0001, X}, Start, WSN);
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flop #(Nf+4) wsflop(clk, WSN, WS);
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mux2 #(Nf+4) wcmux({WCA[54:0], 1'b0}, 56'b0, Start, WCN);
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flop #(Nf+4) wcflop(clk, WCN, WC);
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flopen #(Nf+4) dflop(clk, Start, {4'b0001, Dpreproc}, D);
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mux2 #(`DIVLEN+4) wsmux({WSA[`DIVLEN+2:0], 1'b0}, {4'b0001, X}, Start, WSN);
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flop #(`DIVLEN+4) wsflop(clk, WSN, WS);
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mux2 #(`DIVLEN+4) wcmux({WCA[`DIVLEN+2:0], 1'b0}, {(`DIVLEN+4){1'b0}}, Start, WCN);
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flop #(`DIVLEN+4) wcflop(clk, WCN, WC);
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flopen #(`DIVLEN+4) dflop(clk, Start, {4'b0001, Dpreproc}, D);
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// Quotient Selection logic
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// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
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// Accumulate quotient digits in a shift register
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qsel #(Nf) qsel(WS[55:52], WC[55:52], qp, qz, qm);
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qacc #(Nf+3) qacc(clk, Start, qp, qz, qm, rp, rm);
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qsel2 qsel2(WS[`DIVLEN+3:`DIVLEN], WC[`DIVLEN+3:`DIVLEN], qp, qz, qm);
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// Accumulate quotient digits in a shift register (now done in OTFC)
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qacc #(`DIVLEN+3) qacc(clk, Start, qp, qz, qm, rp, rm);
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flopen #(`NE) expflop(clk, Start, calcExp, rExp);
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flopen #(1) signflop(clk, Start, calcSign, rsign);
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// Divisor Selection logic
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inv dinv(D, Db);
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mux3onehot divisorsel(Db, 56'b0, D, qp, qz, qm, Dsel);
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mux3onehot #(`DIVLEN) divisorsel(Db, {(`DIVLEN+4){1'b0}}, D, qp, qz, qm, Dsel);
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// Partial Product Generation
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csa csa(WS, WC, Dsel, qp, WSA, WCA);
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csa #(`DIVLEN+4) csa(WS, WC, Dsel, qp, WSA, WCA);
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otfc2 otfc2(clk, Start, qp, qz, qm, QuotOTFC);
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otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, QuotOTFC);
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expcalc expcalc(.XExp, .YExp, .calcExp);
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@ -95,70 +101,60 @@ module srt #(parameter Nf=52) (
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srtpostproc postproc(rp, rm, Quot);
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endmodule
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module srtpostproc #(parameter N=52) (
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input [N+2:0] rp, rm,
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output [N-1:0] Quot
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);
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////////////////
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// Submodules //
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////////////////
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//assign Quot = rp - rm;
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finaladd finaladd(rp, rm, Quot);
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endmodule
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module srtpreproc #(parameter Nf=52) (
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///////////////////
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// Preprocessing //
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///////////////////
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module srtpreproc (
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input logic [`XLEN-1:0] SrcA, SrcB,
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input logic [Nf-1:0] SrcXFrac, SrcYFrac,
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input logic [`NF-1:0] SrcXFrac, SrcYFrac,
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input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
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input logic W64, // 32-bit ints on XLEN=64
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input logic Signed, // Interpret integers as signed 2's complement
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input logic Int, // Choose integer inputss
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input logic Int, // Choose integer inputs
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input logic Sqrt, // perform square root, not divide
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output logic [Nf-1:0] X, D
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output logic [`DIVLEN-1:0] X, D,
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output logic [$clog2(`XLEN+1)-1:0] intExp, // Quotient integer exponent
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output logic intSign // Quotient integer sign
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);
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// Initial: just pass X and Y through for simple fp division
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assign X = SrcXFrac;
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assign D = SrcYFrac;
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logic [$clog2(`XLEN+1)-1:0] zeroCntA, zeroCntB;
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logic [`XLEN-1:0] PosA, PosB;
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logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY;
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assign PosA = (Signed & SrcA[`XLEN - 1]) ? -SrcA : SrcA;
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assign PosB = (Signed & SrcB[`XLEN - 1]) ? -SrcB : SrcB;
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lzc #(`XLEN) lzcA (PosA, zeroCntA);
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lzc #(`XLEN) lzcB (PosB, zeroCntB);
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assign ExtraA = {1'b0, PosA, {`EXTRAINTBITS{1'b0}}};
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assign ExtraB = {1'b0, PosB, {`EXTRAINTBITS{1'b0}}};
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assign PreprocA = ExtraA << zeroCntA;
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assign PreprocB = ExtraB << (zeroCntB + 1);
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assign PreprocX = {SrcXFrac, {`EXTRAFRACBITS{1'b0}}};
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assign PreprocY = {SrcYFrac, {`EXTRAFRACBITS{1'b0}}};
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assign X = Int ? PreprocA : PreprocX;
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assign D = Int ? PreprocB : PreprocY;
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assign intExp = zeroCntB - zeroCntA + 1;
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assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]);
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endmodule
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/*
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//////////
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// mux2 //
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//////////
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module mux2(input logic [55:0] in0, in1,
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input logic sel,
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output logic [55:0] out);
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assign #1 out = sel ? in1 : in0;
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endmodule
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//////////
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// flop //
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//////////
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module flop(clk, in, out);
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input clk;
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input [55:0] in;
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output [55:0] out;
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logic [55:0] state;
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always @(posedge clk)
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state <= #1 in;
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assign #1 out = state;
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endmodule
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*/
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//////////
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// qsel //
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//////////
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module qsel #(parameter Nf=52) ( // *** eventually just change to 4 bits
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input logic [Nf+3:Nf] ps, pc,
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/////////////////////////////////
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// Quotient Selection, Radix 2 //
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/////////////////////////////////
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module qsel2 ( // *** eventually just change to 4 bits
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input logic [`DIVLEN+3:`DIVLEN] ps, pc,
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output logic qp, qz, qm
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);
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logic [Nf+3:Nf] p, g;
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logic [`DIVLEN+3:`DIVLEN] p, g;
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logic magnitude, sign, cout;
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// The quotient selection logic is presented for simplicity, not
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@ -169,9 +165,9 @@ module qsel #(parameter Nf=52) ( // *** eventually just change to 4 bits
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assign p = ps ^ pc;
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assign g = ps & pc;
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assign #1 magnitude = ~(&p[54:52]);
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assign #1 cout = g[54] | (p[54] & (g[53] | p[53] & g[52]));
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assign #1 sign = p[55] ^ cout;
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assign #1 magnitude = ~(&p[`DIVLEN+2:`DIVLEN]);
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assign #1 cout = g[`DIVLEN+2] | (p[`DIVLEN+2] & (g[`DIVLEN+1] | p[`DIVLEN+1] & g[`DIVLEN]));
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assign #1 sign = p[`DIVLEN+3] ^ cout;
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/* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) &
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(ps[52]^pc[52]));
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assign #1 sign = (ps[55]^pc[55])^
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@ -188,15 +184,16 @@ endmodule
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//////////
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// qacc //
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//////////
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module qacc #(parameter N=55) (
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// To be replaced by OTFC
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module qacc #(parameter N=68) (
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input logic clk,
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input logic req,
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input logic qp, qz, qm,
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output logic [N-1:0] rp, rm
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);
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flopr #(N) rmreg(clk, req, {rm[53:0], qm}, rm);
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flopr #(N) rpreg(clk, req, {rp[53:0], qp}, rp);
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flopr #(N) rmreg(clk, req, {rm[N-2:0], qm}, rm);
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flopr #(N) rpreg(clk, req, {rp[N-2:0], qp}, rp);
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/* always @(posedge clk)
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begin
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if (req)
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@ -212,11 +209,10 @@ module qacc #(parameter N=55) (
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end */
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endmodule
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//////////
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// otfc //
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//////////
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module otfc2 #(parameter N=52) (
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///////////////////////////////////
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// On-The-Fly Converter, Radix 2 //
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///////////////////////////////////
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module otfc2 #(parameter N=65) (
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input logic clk,
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input logic Start,
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input logic qp, qz, qm,
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@ -255,16 +251,15 @@ module otfc2 #(parameter N=52) (
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QMNext = {QMR, 1'b0};
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end
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end
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assign r = Q[54] ? Q[53:2] : Q[52:1];
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assign r = Q[N+2] ? Q[N+1:2] : Q[N:1];
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endmodule
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/////////
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// inv //
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/////////
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module inv(input logic [55:0] in,
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output logic [55:0] out);
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module inv(input logic [`DIVLEN+3:0] in,
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output logic [`DIVLEN+3:0] out);
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assign #1 out = ~in;
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endmodule
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@ -272,14 +267,11 @@ endmodule
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//////////
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// mux3 //
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//////////
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module mux3onehot(in0, in1, in2, sel0, sel1, sel2, out);
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input [55:0] in0;
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input [55:0] in1;
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input [55:0] in2;
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input sel0;
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input sel1;
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input sel2;
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output [55:0] out;
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module mux3onehot #(parameter N=65) (
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input logic [N+3:0] in0, in1, in2,
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input logic sel0, sel1, sel2,
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output logic [N+3:0] out
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);
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// lazy inspection of the selects
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// really we should make sure selects are mutually exclusive
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@ -290,7 +282,7 @@ endmodule
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/////////
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// csa //
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/////////
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module csa #(parameter N=56) (
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module csa #(parameter N=69) (
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input logic [N-1:0] in1, in2, in3,
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input logic cin,
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output logic [N-1:0] out1, out2
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@ -305,28 +297,26 @@ module csa #(parameter N=56) (
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// insert cin.
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assign #1 out1 = in1 ^ in2 ^ in3;
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assign #1 out2 = {in1[54:0] & (in2[54:0] | in3[54:0]) |
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(in2[54:0] & in3[54:0]), cin};
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assign #1 out2 = {in1[N-2:0] & (in2[N-2:0] | in3[N-2:0]) |
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(in2[N-2:0] & in3[N-2:0]), cin};
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endmodule
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//////////////
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// expcalc //
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//////////////
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module expcalc(
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input logic [`NE-1:0] XExp, YExp,
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output logic [`NE-1:0] calcExp
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);
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assign calcExp = XExp - YExp + 11'b01111111111;
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assign calcExp = XExp - YExp + (`NE)'(`BIAS);
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endmodule
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//////////////
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// signcalc //
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//////////////
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module signcalc(
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input logic XSign, YSign,
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output logic calcSign
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@ -336,15 +326,27 @@ module signcalc(
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endmodule
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////////////////////
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// Postprocessing //
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////////////////////
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module srtpostproc (
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input [`DIVLEN+2:0] rp, rm,
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output [`DIVLEN-1:0] Quot
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);
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//assign Quot = rp - rm;
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finaladd #(`DIVLEN+3) finaladd(rp, rm, Quot);
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endmodule
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//////////////
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// finaladd //
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//////////////
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module finaladd(
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input logic [54:0] rp, rm,
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output logic [51:0] r
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module finaladd #(parameter N=68) (
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input logic [N-1:0] rp, rm,
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output logic [N-4:0] r
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);
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logic [54:0] diff;
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logic [N-1:0] diff;
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// this magic block performs the final addition for you
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// to convert the positive and negative quotient digits
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@ -359,6 +361,6 @@ module finaladd(
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// The checker ignores such an error.
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assign #1 diff = rp - rm;
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assign #1 r = diff[54] ? diff[53:2] : diff[52:1];
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assign #1 r = diff[N-1] ? diff[N-2:2] : diff[N-3:1];
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endmodule
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@ -1,3 +1,5 @@
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`define DIVLEN 65
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/////////////
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// counter //
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/////////////
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@ -45,6 +47,7 @@ module testbench;
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logic [10:0] aExp, bExp;
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logic asign, bsign;
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logic [51:0] r, rOTFC;
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logic [`DIVLEN-1:0] Quot, QuotOTFC;
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logic [54:0] rp, rm; // positive quotient digits
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// Test parameters
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@ -65,14 +68,14 @@ module testbench;
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integer testnum, errors;
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// Divider
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srt #(52) srt(.clk, .Start(req),
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srt srt(.clk, .Start(req),
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.Stall(1'b0), .Flush(1'b0),
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.XExp(aExp), .YExp(bExp), .rExp,
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.XSign(asign), .YSign(bsign), .rsign,
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.SrcXFrac(afrac), .SrcYFrac(bfrac),
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.SrcA('0), .SrcB('0), .Fmt(2'b00),
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.W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0),
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.Quot(r), .QuotOTFC(rOTFC), .Rem(), .Flags());
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.Quot, .QuotOTFC, .Rem(), .Flags());
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// Counter
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counter counter(clk, req, done);
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@ -98,6 +101,8 @@ module testbench;
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b = Vec[`memb];
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{bsign, bExp, bfrac} = b;
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nextr = Vec[`memr];
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r = Quot[`DIVLEN:`DIVLEN - 52];
|
||||
rOTFC = QuotOTFC[`DIVLEN:`DIVLEN - 52];
|
||||
req <= #5 1;
|
||||
end
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user