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BTB cleanup.

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This commit is contained in:
Ross Thompson 2023-01-25 12:05:13 -06:00
parent 7e1363bfad
commit afdcfeb93b
2 changed files with 11 additions and 37 deletions
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2
pipelined/src/ifu/brpred/bpred.sv
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@ -143,7 +143,7 @@ module bpred (
.InstrClass(PredInstrClassF), .InstrClass(PredInstrClassF),
.Valid(BTBValidF), .Valid(BTBValidF),
// update // update
.UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE), .UpdateEN(|InstrClassE | PredictionInstrClassWrongE),
.PCE, .PCE,
.IEUAdrE, .IEUAdrE,
.UpdateInvalid(PredictionInstrClassWrongE), .UpdateInvalid(PredictionInstrClassWrongE),

46
pipelined/src/ifu/brpred/btb.sv
View File

@ -35,7 +35,7 @@ module btb
) )
(input logic clk, (input logic clk,
input logic reset, input logic reset,
input logic StallF, StallE, input logic StallF, StallE, StallM, FlushM,
input logic [`XLEN-1:0] PCNextF, input logic [`XLEN-1:0] PCNextF,
output logic [`XLEN-1:0] BTBPredPCF, output logic [`XLEN-1:0] BTBPredPCF,
output logic [3:0] InstrClass, output logic [3:0] InstrClass,
@ -50,7 +50,7 @@ module btb
localparam TotalDepth = 2 ** Depth; localparam TotalDepth = 2 ** Depth;
logic [TotalDepth-1:0] ValidBits; logic [TotalDepth-1:0] ValidBits;
logic [Depth-1:0] PCNextFIndex, PCEIndex, PCNextFIndexQ, PCEIndexQ; logic [Depth-1:0] PCNextFIndex, PCEIndex;
logic UpdateENQ; logic UpdateENQ;
logic [`XLEN-1:0] ResetPC; logic [`XLEN-1:0] ResetPC;
@ -60,51 +60,25 @@ module btb
// bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
// using compressed instructions. XOR bit 1 with the MSB of index. // using compressed instructions. XOR bit 1 with the MSB of index.
assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]}; assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]};
// must output a valid PC and valid bit during reset. Because the PCNextF logic of the IFU and trap units
// does not mux in RESET_VECTOR we have to do it here. This is a performance optimization.
assign ResetPC = `RESET_VECTOR; assign ResetPC = `RESET_VECTOR;
assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};
//assign PCNextFIndex = {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};
flopenr #(Depth) PCEIndexReg(.clk(clk),
.reset(reset),
.en(~StallE),
.d(PCEIndex),
.q(PCEIndexQ));
// The valid bit must be resetable.
always_ff @ (posedge clk) begin always_ff @ (posedge clk) begin
if (reset) begin if (reset) begin
ValidBits <= #1 {TotalDepth{1'b0}}; ValidBits <= #1 {TotalDepth{1'b0}};
end else end else if (UpdateEN & ~StallM & ~FlushM) begin
if (UpdateENQ) begin ValidBits[PCEIndex] <= #1 ~ UpdateInvalid;
ValidBits[PCEIndexQ] <= #1 ~ UpdateInvalid;
end end
Valid = ValidBits[PCNextFIndex];
end end
assign Valid = ValidBits[PCNextFIndexQ];
// An optimization may be using a PC relative address.
flopenr #(1) UpdateENReg(.clk(clk),
.reset(reset),
.en(~StallF),
.d(UpdateEN),
.q(UpdateENQ));
flopenr #(Depth) LookupPCIndexReg(.clk(clk),
.reset(reset),
.en(~StallF),
.d(PCNextFIndex),
.q(PCNextFIndexQ));
// the BTB contains the target address.
// Another optimization may be using a PC relative address.
// *** need to add forwarding. // *** need to add forwarding.
// *** optimize for byte write enables
ram2p1r1wbe #(2**Depth, `XLEN+4) memory( ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
.clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}), .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}),
.ce2(~StallE), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1));
endmodule endmodule