forked from Github_Repos/cvw
Another round of cleanup in the LSU.
This commit is contained in:
Ross Thompson
parent
a60a1756a4
commit
af6899472d
@ -32,107 +32,107 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module lsu (
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module lsu (
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input logic clk, reset,
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input logic clk,set,
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input logic StallM, FlushM, StallW, FlushW,
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input logic StallM,ushM, StallW, FlushW,
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output logic LSUStallM, // LSU stalls pipeline during a multicycle operation
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output logic LSUStallM, // LSU stalls pipeline during a multicycle operation
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// connected to cpu (controls)
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// connected to cpu (controls)
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input logic [1:0] MemRWM, // Read/Write control
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input logic [1:0] MemRWM, // Read/Write control
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input logic [2:0] Funct3M, // Size of memory operation
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input logic [2:0] Funct3M, // Size of memory operation
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input logic [6:0] Funct7M, // Atomic memory operation function
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input logic [6:0] Funct7M, // Atomic memory operation function
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input logic [1:0] AtomicM, // Atomic memory operation
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input logic [1:0] AtomicM, // Atomic memory operation
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input logic FlushDCacheM, // Flush D cache to next level of memory
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input logic FlushDCacheM, // Flush D cache to next level of memory
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output logic CommittedM, // Delay interrupts while memory operation in flight
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output logic CommittedM, // Delay interrupts while memory operation in flight
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output logic SquashSCW, // Store conditional failed disable write to GPR
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output logic SquashSCW, // Store conditional failed disable write to GPR
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output logic DCacheMiss, // D cache miss for performance counters
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output logic DCacheMiss, // D cache miss for performance counters
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output logic DCacheAccess, // D cache memory access for performance counters
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output logic DCacheAccess, // D cache memory access for performance counters
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// address and write data
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// address and write data
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input logic [`XLEN-1:0] IEUAdrE, // Execution stage memory address
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input logic [`XLEN-1:0] IEUAdrE, // Execution stage memory address
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output logic [`XLEN-1:0] IEUAdrM, // Memory stage memory address
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output logic [`XLEN-1:0] IEUAdrM, // Memory stage memory address
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input logic [`XLEN-1:0] WriteDataM, // Write data from IEU
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input logic [`XLEN-1:0] WriteDataM, // Write data from IEU
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output logic [`LLEN-1:0] ReadDataW, // Read data to IEU or FPU
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output logic [`LLEN-1:0] ReadDataW, // Read data to IEU or FPU
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// cpu privilege
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// cpu privilege
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input logic [1:0] PrivilegeModeW, // Current privilege mode
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input logic [1:0] PrivilegeModeW, // Current privilege mode
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input logic BigEndianM, // Swap byte order to big endian
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input logic BigEndianM, // Swap byte order to big endian
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input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
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input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
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// fpu
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// fpu
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input logic [`FLEN-1:0] FWriteDataM, // Write data from FPU
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input logic [`FLEN-1:0] FWriteDataM, // Write data from FPU
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input logic FpLoadStoreM, // Selects FPU as store for write data
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input logic FpLoadStoreM, // Selects FPU as store for write data
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// faults
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// faults
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output logic LoadPageFaultM, StoreAmoPageFaultM, // Page fault exceptions
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output logic LoadPageFaultM,oreAmoPageFaultM, // Page fault exceptions
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output logic LoadMisalignedFaultM, // Load address misaligned fault
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output logic LoadMisalignedFaultM, // Load address misaligned fault
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output logic LoadAccessFaultM, // Load access fault (PMA)
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output logic LoadAccessFaultM, // Load access fault (PMA)
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output logic HPTWInstrAccessFaultM, // HPTW generated access fault during instruction fetch
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output logic HPTWInstrAccessFaultM, // HPTW generated access fault during instruction fetch
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// cpu hazard unit (trap)
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// cpu hazard unit (trap)
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output logic StoreAmoMisalignedFaultM, // Store or AMO address misaligned fault
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output logic StoreAmoMisalignedFaultM, // Store or AMO address misaligned fault
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output logic StoreAmoAccessFaultM, // Store or AMO access fault
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output logic StoreAmoAccessFaultM, // Store or AMO access fault
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// connect to ahb
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// connect to ahb
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output logic [`PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU
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output logic [`PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU
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input logic [`XLEN-1:0] HRDATA, // Bus read data from LSU to EBU
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input logic [`XLEN-1:0] HRDATA, // Bus read data from LSU to EBU
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output logic [`XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU
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output logic [`XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU
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input logic LSUHREADY, // Bus ready from LSU to EBU
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input logic LSUHREADY, // Bus ready from LSU to EBU
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output logic LSUHWRITE, // Bus write operation from LSU to EBU
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output logic LSUHWRITE, // Bus write operation from LSU to EBU
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output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU
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output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU
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output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU
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output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU
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output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU
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output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU
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output logic [`XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU
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output logic [`XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU
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// page table walker
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// page table walker
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input logic [`XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR
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input logic [`XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
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input logic STATUS_MXR,ATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
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input logic [1:0] STATUS_MPP, // Machine previous privilege mode
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input logic [1:0] STATUS_MPP, // Machine previous privilege mode
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input logic [`XLEN-1:0] PCF, // Fetch PC
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input logic [`XLEN-1:0] PCF, // Fetch PC
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input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
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input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
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input logic InstrDAPageFaultF, // ITLB hit needs to update dirty or access bits
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input logic InstrDAPageFaultF, // ITLB hit needs to update dirty or access bits
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output logic [`XLEN-1:0] PTE, // Page table entry write to ITLB
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output logic [`XLEN-1:0] PTE, // Page table entry write to ITLB
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output logic [1:0] PageType, // Type of page table entry to write to ITLB
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output logic [1:0] PageType, // Type of page table entry to write to ITLB
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output logic ITLBWriteF, // Write PTE to ITLB
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output logic ITLBWriteF, // Write PTE to ITLB
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output logic SelHPTW, // During a HPTW walk the effective privilege mode becomes S_MODE
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output logic SelHPTW, // During a HPTW walk the effective privilege mode becomes S_MODE
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration from privileged unit
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input var logic [7:0] PMPCFG_ARRAY_REGW[P_ENTRIES-1:0], // PMP configuration from privileged unit
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP address from privileged unit
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP address from privileged unit
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);
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);
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logic [`XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
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logic [`XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer
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logic [`XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
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logic [`XLEN+1:0] IEUAdrExtE; // Execution stage address zero-extended to PA_BITS or XLEN whichever is longer
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logic [`PA_BITS-1:0] PAdrM; // Physical memory address
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logic [`PA_BITS-1:0] PAdrM; // Physical memory address
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logic [`XLEN+1:0] IHAdrM; // Either IEU or HPTW memory address
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logic [`XLEN+1:0] IHAdrM; // Either IEU or HPTW memory address
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logic [1:0] PreLSURWM; // IEU or HPTW Read/Write signal
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logic [1:0] PreLSURWM; // IEU or HPTW Read/Write signal
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logic [1:0] LSURWM; // IEU or HPTW Read/Write signal gated by LR/SC
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logic [1:0] LSURWM; // IEU or HPTW Read/Write signal gated by LR/SC
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logic [2:0] LSUFunct3M; // IEU or HPTW memory operation size
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logic [2:0] LSUFunct3M; // IEU or HPTW memory operation size
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logic [6:0] LSUFunct7M; // AMO function gated by HPTW
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logic [6:0] LSUFunct7M; // AMO function gated by HPTW
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logic [1:0] LSUAtomicM; // AMO signal gated by HPTW
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logic [1:0] LSUAtomicM; // AMO signal gated by HPTW
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logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1
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logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1
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logic DCacheStallM; // D$ busy with multicycle operation
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logic DCacheStallM; // D$ busy with multicycle operation
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logic BusStall; // Bus interface busy with multicycle operation
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logic BusStall; // Bus interface busy with multicycle operation
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logic HPTWStall; // HPTW busy with multicycle operation
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logic HPTWStall; // HPTW busy with multicycle operation
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logic CacheableM; // PMA indicates memory address is cacheable
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logic CacheableM; // PMA indicates memory address is cacheable
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logic BusCommittedM; // Bus memory operation in flight, delay interrupts
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logic BusCommittedM; // Bus memory operation in flight, delay interrupts
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logic DCacheCommittedM; // D$ memory operation started, delay interrupts
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logic DCacheCommittedM; // D$ memory operation started, delay interrupts
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logic [`LLEN-1:0] DTIMReadDataWordM; // DTIM read data
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logic [`LLEN-1:0] DTIMReadDataWordM; // DTIM read data
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logic [`LLEN-1:0] DCacheReadDataWordM; // D$ read data
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logic [`LLEN-1:0] DCacheReadDataWordM; // D$ read data
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logic [`LLEN-1:0] ReadDataWordMuxM; // DTIM or D$ read data
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logic [`LLEN-1:0] ReadDataWordMuxM; // DTIM or D$ read data
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logic [`LLEN-1:0] LittleEndianReadDataWordM; // Endian-swapped read data
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logic [`LLEN-1:0] LittleEndianReadDataWordM; // Endian-swapped read data
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logic [`LLEN-1:0] ReadDataWordM; // Read data before subword selection
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logic [`LLEN-1:0] ReadDataWordM; // Read data before subword selection
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logic [`LLEN-1:0] ReadDataM; // Final read data
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logic [`LLEN-1:0] ReadDataM; // Final read data
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logic [`XLEN-1:0] IHWriteDataM; // IEU or HPTW write data
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logic [`XLEN-1:0] IHWriteDataM; // IEU or HPTW write data
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logic [`XLEN-1:0] IMAWriteDataM; // IEU, HPTW, or AMO write data
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logic [`XLEN-1:0] IMAWriteDataM; // IEU, HPTW, or AMO write data
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logic [`LLEN-1:0] IMAFWriteDataM; // IEU, HPTW, AMO, or FPU write data
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logic [`LLEN-1:0] IMAFWriteDataM; // IEU, HPTW, AMO, or FPU write data
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logic [`LLEN-1:0] LittleEndianWriteDataM; // Ending-swapped write data
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logic [`LLEN-1:0] LittleEndianWriteDataM; // Ending-swapped write data
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logic [`LLEN-1:0] LSUWriteDataM; // Final write data
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logic [`LLEN-1:0] LSUWriteDataM; // Final write data
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logic [(`LLEN-1)/8:0] ByteMaskM; // Selects which bytes within a word to write
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logic [(`LLEN-1)/8:0] ByteMaskM; // Selects which bytes within a word to write
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logic DTLBMissM; // DTLB miss causes HPTW walk
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logic DTLBMissM; // DTLB miss causes HPTW walk
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logic DTLBWriteM; // Writes PTE and PageType to DTLB
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logic DTLBWriteM; // Writes PTE and PageType to DTLB
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logic DataDAPageFaultM; // DTLB hit needs to update dirty or access bits
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logic DataDAPageFaultM; // DTLB hit needs to update dirty or access bits
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logic LSULoadAccessFaultM; // Load acces fault
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logic LSULoadAccessFaultM; // Load acces fault
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logic LSUStoreAmoAccessFaultM; // Store access fault
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logic LSUStoreAmoAccessFaultM; // Store access fault
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logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle
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logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle
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logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation
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logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation
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logic SelDTIM; // Select DTIM rather than bus or D$
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logic SelDTIM; // Select DTIM rather than bus or D$
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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