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This commit is contained in:
Ross Thompson 2021-06-24 13:05:22 -05:00
parent c8f80967a6
commit aeeaf6d919
7 changed files with 335 additions and 234 deletions
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3
wally-pipelined/config/busybear/wally-config.vh
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@ -30,7 +30,8 @@
`define BUILDROOT 0 `define BUILDROOT 0
`define BUSYBEAR 1 `define BUSYBEAR 1
`define LINUX_FIX_READ {'h10000005} `define LINUX_FIX_READ {'h10000005}
`define LINUX_TEST_VECTORS "/courses/e190ax/busybear_boot/" `define LINUX_TEST_VECTORS "../../../busybear_boot/"
//`define LINUX_TEST_VECTORS "/courses/e190ax/busybear_boot/"
// RV32 or RV64: XLEN = 32 or 64 // RV32 or RV64: XLEN = 32 or 64
`define XLEN 64 `define XLEN 64

4
wally-pipelined/src/ebu/ahblite.sv
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@ -80,7 +80,6 @@ module ahblite (
output logic [3:0] HSIZED, output logic [3:0] HSIZED,
output logic HWRITED, output logic HWRITED,
// Stalls // Stalls
output logic /*InstrUpdate, */DataStall,
output logic CommitM, MemAckW output logic CommitM, MemAckW
); );
@ -152,9 +151,12 @@ module ahblite (
// stall signals // stall signals
// Note that we need to extend both stalls when MMUTRANSLATE goes to idle, // Note that we need to extend both stalls when MMUTRANSLATE goes to idle,
// since translation might not be complete. // since translation might not be complete.
// *** Ross Thompson remove this datastall
/* -----\/----- EXCLUDED -----\/-----
assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || assign #2 DataStall = ((NextBusState == MEMREAD) || (NextBusState == MEMWRITE) ||
(NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) || (NextBusState == ATOMICREAD) || (NextBusState == ATOMICWRITE) ||
MMUStall); MMUStall);
-----/\----- EXCLUDED -----/\----- */
//assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) || //assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
// MMUStall); // MMUStall);

26
wally-pipelined/src/hazard/hazard.sv
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@ -31,7 +31,7 @@ module hazard(
// Detect hazards // Detect hazards
input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM, input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
input logic LoadStallD, MulDivStallD, CSRRdStallD, input logic LoadStallD, MulDivStallD, CSRRdStallD,
input logic DataStall, ICacheStallF, input logic DCacheStall, ICacheStallF,
input logic FPUStallD, input logic FPUStallD,
input logic DivBusyE,FDivBusyE, input logic DivBusyE,FDivBusyE,
// Stall & flush outputs // Stall & flush outputs
@ -55,16 +55,16 @@ module hazard(
// A stage must stall if the next stage is stalled // A stage must stall if the next stage is stalled
// If any stages are stalled, the first stage that isn't stalled must flush. // If any stages are stalled, the first stage that isn't stalled must flush.
assign StallFCause = CSRWritePendingDEM && ~(TrapM || RetM || BPPredWrongE); assign StallFCause = CSRWritePendingDEM && ~(TrapM | RetM | BPPredWrongE);
assign StallDCause = (LoadStallD || MulDivStallD || CSRRdStallD || FPUStallD) && ~(TrapM || RetM || BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous assign StallDCause = (LoadStallD | MulDivStallD | CSRRdStallD | FPUStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous
assign StallECause = DivBusyE || FDivBusyE; assign StallECause = DivBusyE | FDivBusyE;
assign StallMCause = 0; assign StallMCause = 0;
assign StallWCause = DataStall || ICacheStallF; assign StallWCause = DCacheStall | ICacheStallF;
assign StallF = StallFCause || StallD; assign StallF = StallFCause | StallD;
assign StallD = StallDCause || StallE; assign StallD = StallDCause | StallE;
assign StallE = StallECause || StallM; assign StallE = StallECause | StallM;
assign StallM = StallMCause || StallW; assign StallM = StallMCause | StallW;
assign StallW = StallWCause; assign StallW = StallWCause;
//assign FirstUnstalledD = (~StallD & StallF & ~MulDivStallD); //assign FirstUnstalledD = (~StallD & StallF & ~MulDivStallD);
@ -76,8 +76,8 @@ module hazard(
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
assign FlushF = BPPredWrongE; assign FlushF = BPPredWrongE;
assign FlushD = FirstUnstalledD || TrapM || RetM || BPPredWrongE; assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE;
assign FlushE = FirstUnstalledE || TrapM || RetM || BPPredWrongE; assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE;
assign FlushM = FirstUnstalledM || TrapM || RetM; assign FlushM = FirstUnstalledM | TrapM | RetM;
assign FlushW = FirstUnstalledW || TrapM; assign FlushW = FirstUnstalledW | TrapM;
endmodule endmodule

27
wally-pipelined/src/ifu/ifu.sv
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@ -78,7 +78,6 @@ module ifu (
input logic [31:0] HADDR, input logic [31:0] HADDR,
input logic [2:0] HSIZE, input logic [2:0] HSIZE,
input logic HWRITE, input logic HWRITE,
input logic ExecuteAccessF, //read, write, and atomic access are all set to zero because this mmu is onlt working with instructinos in the F stage.
input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so they're gonna have to come over into ifu and dmem input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so they're gonna have to come over into ifu and dmem
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
@ -114,14 +113,24 @@ module ifu (
assign PCPF = {8'b0, PCPFmmu}; assign PCPF = {8'b0, PCPFmmu};
endgenerate endgenerate
mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF), .Size(2'b10), mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1))
.PTEWriteVal(PageTableEntryF), .PageTypeWriteVal(PageTypeF), itlb(.TLBAccessType(2'b10),
.TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF), .VirtualAddress(PCF),
.PhysicalAddress(PCPFmmu), .TLBMiss(ITLBMissF), .Size(2'b10),
.TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF), .PTEWriteVal(PageTableEntryF),
.PageTypeWriteVal(PageTypeF),
.AtomicAccessM(1'b0), .WriteAccessM(1'b0), .ReadAccessM(1'b0), // *** is this the right way force these bits constant? should they be someething else? .TLBWrite(ITLBWriteF),
.SquashBusAccess(ISquashBusAccessF), .HSELRegions(IHSELRegionsF), .TLBFlush(ITLBFlushF),
.PhysicalAddress(PCPFmmu),
.TLBMiss(ITLBMissF),
.TLBHit(ITLBHitF),
.TLBPageFault(ITLBInstrPageFaultF),
.ExecuteAccessF(1'b1),
.AtomicAccessM(1'b0),
.WriteAccessM(1'b0),
.ReadAccessM(1'b0),
.SquashBusAccess(ISquashBusAccessF),
.HSELRegions(IHSELRegionsF),
.DisableTranslation(1'b0), .DisableTranslation(1'b0),
.*); .*);

28
wally-pipelined/src/lsu/lsu.sv
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@ -31,7 +31,7 @@
module lsu ( module lsu (
input logic clk, reset, input logic clk, reset,
input logic StallM, FlushM, StallW, FlushW, input logic StallM, FlushM, StallW, FlushW,
//output logic DataStall, output logic DataStall,
// Memory Stage // Memory Stage
// connected to cpu (controls) // connected to cpu (controls)
@ -115,14 +115,24 @@ module lsu (
// CPU's read data input ReadDataW. // CPU's read data input ReadDataW.
assign ReadDataW = HRDATAW; assign ReadDataW = HRDATAW;
mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM), .Size(Funct3M[1:0]), mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0))
.PTEWriteVal(PageTableEntryM), .PageTypeWriteVal(PageTypeM), dmmu(.TLBAccessType(MemRWM),
.TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM), .VirtualAddress(MemAdrM),
.PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM), .Size(Funct3M[1:0]),
.TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM), .PTEWriteVal(PageTableEntryM),
.PageTypeWriteVal(PageTypeM),
.TLBWrite(DTLBWriteM),
.TLBFlush(DTLBFlushM),
.PhysicalAddress(MemPAdrM),
.TLBMiss(DTLBMissM),
.TLBHit(DTLBHitM),
.TLBPageFault(DTLBPageFaultM),
.ExecuteAccessF(1'b0), .ExecuteAccessF(1'b0),
.SquashBusAccess(DSquashBusAccessM), .HSELRegions(DHSELRegionsM), .AtomicAccessM(|AtomicM),
.WriteAccessM(MemRWM[0]),
.ReadAccessM(MemRWM[1]),
.SquashBusAccess(DSquashBusAccessM),
.HSELRegions(DHSELRegionsM),
.*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
// Specify which type of page fault is occurring // Specify which type of page fault is occurring
@ -185,7 +195,7 @@ module lsu (
endgenerate endgenerate
// Data stall // Data stall
//assign DataStall = 0; assign DataStall = CurrState != STATE_READY;
// Ross Thompson April 22, 2021 // Ross Thompson April 22, 2021
// for now we need to handle the issue where the data memory interface repeately // for now we need to handle the issue where the data memory interface repeately

125
wally-pipelined/src/lsu/lsuArb.sv
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@ -26,77 +26,112 @@
`include "wally-config.vh" `include "wally-config.vh"
module lsuArb ( module lsuArb
input logic clk, reset, (input logic clk, reset,
// signals from page table walker // from page table walker
// output logic [`XLEN-1:0] MMUReadPTE, // *** it seems like this is the value out of the ahblite that gets sent back to the ptw. I don;t think it needs to get checked until the next paddr has been extracted from it. input logic HPTWTranslate,
input logic MMUTranslate, // *** rename to HPTWReq input logic [`XLEN-1:0] HPTWPAdr,
// output logic MMUReady, // *** Similar reason to mmuReadPTE // to page table walker.
input logic [`XLEN-1:0] MMUPAdr, output logic [`XLEN-1:0] HPTWReadPTE,
output logic HPTWReady,
// signal from CPU // from CPU
input logic [1:0] MemRWM, input logic [1:0] MemRWM,
input logic [2:0] Funct3M, input logic [2:0] Funct3M,
input logic [1:0] AtomicM, input logic [1:0] AtomicM,
input logic [`XLEN-1:0] MemAdrM, // memory addrress to be checked coming from the CPU. *** this will be used to arbitrate to decide HADDR going into the PM checks, but it also gets sent in its normal form to the lsu because we need the virtual address for the tlb. input logic [`XLEN-1:0] MemAdrM,
// back to CPU input logic [`XLEN-1:0] WriteDataM,
// to CPU
/* *** unused for not (23 June 2021) output logic [`XLEN-1:0] ReadDataW,
output logic CommittedM, output logic CommittedM,
output logic SquashSCW, output logic SquashSCW,
output logic DataMisalignedM, output logic DataMisalignedM,
*/ output logic DCacheStall,
// to LSU // to LSU
output logic DisableTranslation, output logic DisableTranslation,
output logic [1:0] MemRWMtoLSU, output logic [1:0] MemRWMtoLSU,
output logic [2:0] Funct3MtoLSU, output logic [2:0] Funct3MtoLSU,
output logic [1:0] AtomicMtoLSU output logic [1:0] AtomicMtoLSU,
output logic [`XLEN-1:0] MemAdrMtoLSU,
output logic [`XLEN-1:0] WriteDataMtoLSU,
// from LSU
input logic CommittedMfromLSU,
input logic SquashSCWfromLSU,
input logic DataMisalignedMfromLSU,
input logic [`XLEN-1:0] ReadDataWFromLSU,
input logic DataStall
/* *********** KMG: A lot of the rest of the signals that need to be arbitrated are going to be very annoying );
these are the ones that used to get sent from the ahb to the pma checkers. but our eventual
goal is to have many of them sent thru the pmp/pma FIRST before the bus can get to them.
deciding how to choose the right Haddr for the PM checkers will be difficult since they currently get // HPTWTranslate is the request for memory by the page table walker. When
HADDR from the ahblite which seems like it could come from any number of sources, while we will eventually be narrowing it down to two possible sources. // this is high the page table walker gains priority over the CPU's data
// input. Note the ptw only makes a request after an instruction or data
// tlb miss. It is entirely possible the dcache is currently processing
// a data cache miss when an instruction tlb miss occurs. If an instruction
// in the E stage causes a d cache miss, the d cache will immediately start
// processing the request. Simultaneously the ITLB misses. By the time
// the TLB miss causes the page table walker to issue the first request
// to data memory the d cache is already busy. We can interlock by
// leveraging Stall as a d cache busy. We will need an FSM to handle this.
other problems arise when some signals like HSIZE are used in the PM checks but there's also a differnent size input to the tlb and both of these get to go through the mmu. localparam StateReady = 0;
which one should be chosen for which device? can the be merged somehow? localparam StatePTWPending = 1;
localparam StatePTWActive = 1;
*/ logic [1:0] CurrState, NextState;
logic SelPTW;
/*// pmp/pma specifics sent through lsu
output logic [`XLEN-1:0] HADDRtoLSU,
output logic [2:0] HSIZEtoLSU // *** May not actually need to be arbitrated, since I'm
*/
);
/* *** these are all the signals that get sent to the pmp/pma chackers straight from the ahblite. We want to switch it around so the flopr #(2) StateReg(
checkers get these signals first and then the newly checked values can get sent to the ahblite. .clk(clk),
input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well. .reset(reset),
input logic [2:0] HSIZE, .d(NextState),
input logic HWRITE, .q(CurrState));
input logic AtomicAccessM, WriteAccessM, ReadAccessM, // execute access is hardwired to zero in this mmu because we're only working with data in the M stage.
*/ always_comb begin
case(CurrState)
StateReady:
if (HPTWTranslate & DataStall) NextState = StatePTWPending;
else if (HPTWTranslate & ~DataStall) NextState = StatePTWActive;
else NextState = StateReady;
StatePTWPending:
if (~DataStall) NextState = StatePTWActive;
else NextState = StatePTWPending;
StatePTWActive:
if (~DataStall) NextState = StateReady;
else NextState = StatePTWActive;
default: NextState = StateReady;
endcase // case (CurrState)
end
// multiplex the outputs to LSU
assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
assign SelPTW = CurrState == StatePTWActive;
assign MemRWMtoLSU = SelPTW ? 2'b10 : MemRWM;
generate generate
if (`XLEN == 32) begin if (`XLEN == 32) begin
assign Funct3MtoLSU = SelPTW ? 3'b010 : Funct3M;
assign Funct3MtoLSU = MMUTranslate ? 3'b010 : Funct3M; // *** is this the right thing for the msB?
end else begin end else begin
assign Funct3MtoLSU = SelPTW ? 3'b011 : Funct3M;
assign Funct3MtoLSU = MMUTranslate ? 3'b011 : Funct3M; // *** is this the right thing for the msB?
end end
endgenerate endgenerate
assign AtomicMtoLSU = MMUTranslate ? 2'b00 : AtomicM; assign AtomicMtoLSU = SelPTW ? 2'b00 : AtomicM;
assign MemRWMtoLSU = MemRWM; // *** along with the rest of the lsu, the mmu uses memrwm in it's pure form so I think we can just forward it through assign MemAdrMtoLSU = SelPTW ? HPTWPAdr : MemAdrM;
assign DisableTranslation = MMUTranslate; assign WriteDataMtoLSU = SelPTW ? `XLEN'b0 : WriteDataM;
// assign HADDRtoLSU = MMUTranslate ? MMUPAdr : MemAdrM; // *** Potentially a huge breaking point since the PM checks always get HADDR from ahblite and not necessarily just these two sources. this will need to be looked over when we fix PM to only take physical addresses.
// assign HSIZEtoLSU = {1'b0, Funct3MtoLSU[1:0]}; // the Hsize is always just the funct3M indicating the size of the data transfer.
// demux the inputs from LSU to walker or cpu's data port.
assign ReadDataW = SelPTW ? `XLEN'b0 : ReadDataWFromLSU; // probably can avoid this demux
assign HPTWReadPTE = SelPTW ? ReadDataWFromLSU : `XLEN'b0 ; // probably can avoid this demux
assign CommittedM = SelPTW ? 1'b0 : CommittedMfromLSU;
assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromLSU;
assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromLSU;
assign HPTWReady = ~ DataStall;
assign DCacheStall = DataStall; // *** this is probably going to change.
endmodule endmodule

72
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -26,10 +26,11 @@
`include "wally-config.vh" `include "wally-config.vh"
/* verilator lint_on UNUSED */ /* verilator lint_on UNUSED */
module wallypipelinedhart ( module wallypipelinedhart
(
input logic clk, reset, input logic clk, reset,
output logic [`XLEN-1:0] PCF, output logic [`XLEN-1:0] PCF,
// input logic [31:0] InstrF, // input logic [31:0] InstrF,
// Privileged // Privileged
input logic TimerIntM, ExtIntM, SwIntM, input logic TimerIntM, ExtIntM, SwIntM,
input logic InstrAccessFaultF, input logic InstrAccessFaultF,
@ -53,7 +54,7 @@ module wallypipelinedhart (
output logic [2:0] HADDRD, output logic [2:0] HADDRD,
output logic [3:0] HSIZED, output logic [3:0] HSIZED,
output logic HWRITED output logic HWRITED
); );
// logic [1:0] ForwardAE, ForwardBE; // logic [1:0] ForwardAE, ForwardBE;
logic StallF, StallD, StallE, StallM, StallW; logic StallF, StallD, StallE, StallM, StallW;
@ -126,6 +127,7 @@ module wallypipelinedhart (
// IMem stalls // IMem stalls
logic ICacheStallF; logic ICacheStallF;
logic DCacheStall;
logic [`XLEN-1:0] MMUPAdr, MMUReadPTE; logic [`XLEN-1:0] MMUPAdr, MMUReadPTE;
logic MMUStall; logic MMUStall;
logic MMUTranslate, MMUReady; logic MMUTranslate, MMUReady;
@ -150,7 +152,7 @@ module wallypipelinedhart (
logic RASPredPCWrongM; logic RASPredPCWrongM;
logic BPPredClassNonCFIWrongM; logic BPPredClassNonCFIWrongM;
logic[`XLEN-1:0] WriteDatatmpM; logic [`XLEN-1:0] WriteDatatmpM;
logic [4:0] InstrClassM; logic [4:0] InstrClassM;
@ -161,6 +163,15 @@ module wallypipelinedhart (
logic [1:0] MemRWMtoLSU; logic [1:0] MemRWMtoLSU;
logic [2:0] Funct3MtoLSU; logic [2:0] Funct3MtoLSU;
logic [1:0] AtomicMtoLSU; logic [1:0] AtomicMtoLSU;
logic [`XLEN-1:0] MemAdrMtoLSU;
logic [`XLEN-1:0] WriteDataMtoLSU;
logic [`XLEN-1:0] ReadDataWFromLSU;
logic CommittedMfromLSU;
logic SquashSCWfromLSU;
logic DataMisalignedMfromLSU;
ifu ifu(.InstrInF(InstrRData), .*); // instruction fetch unit: PC, branch prediction, instruction cache ifu ifu(.InstrInF(InstrRData), .*); // instruction fetch unit: PC, branch prediction, instruction cache
@ -181,17 +192,50 @@ module wallypipelinedhart (
// arbiter between IEU and pagetablewalker // arbiter between IEU and pagetablewalker
lsuArb arbiter(.MMUTranslate(MMUTranslate), .MMUPAdr(MMUPAdr), .MemRWM(MemRWM|FMemRWM), lsuArb arbiter(// HPTW connection
.Funct3M(Funct3M), .AtomicM(AtomicM), .MemAdrM(MemAdrM), .HPTWTranslate(MMUTranslate),
// outputs to LSU .HPTWPAdr(MMUPAdr),
.DisableTranslation(DisableTranslation), .MemRWMtoLSU(MemRWMtoLSU), .Funct3MtoLSU(Funct3MtoLSU), .HPTWReadPTE(MMUReadPTE),
.AtomicMtoLSU(AtomicMtoLSU), .*); .HPTWReady(MMUReady),
// CPU connection
.MemRWM(MemRWM|FMemRWM),
lsu lsu(.MemRWM(MemRWMtoLSU), .AtomicM(AtomicMtoLSU), .Funct3M(Funct3MtoLSU), .Funct3M(Funct3M),
.DisableTranslation(DisableTranslation), .AtomicM(AtomicM),
.MemAdrM(MemAdrM),
.WriteDataM(WriteDatatmpM), .WriteDataM(WriteDatatmpM),
.ReadDataW(ReadDataW), .* ); // data cache unit .ReadDataW(ReadDataW),
.CommittedM(CommittedM),
.SquashSCW(SquashSCW),
.DataMisalignedM(DataMisalignedM),
.DCacheStall(DCacheStall),
// LSU
.DisableTranslation(DisableTranslation),
.MemRWMtoLSU(MemRWMtoLSU),
.Funct3MtoLSU(Funct3MtoLSU),
.AtomicMtoLSU(AtomicMtoLSU),
.MemAdrMtoLSU(MemAdrMtoLSU),
.WriteDataMtoLSU(WriteDataMtoLSU),
.CommittedMfromLSU(CommittedMfromLSU),
.SquashSCWfromLSU(SquashSCWfromLSU),
.DataMisalignedMfromLSU(DataMisalignedMfromLSU),
.ReadDataWFromLSU(ReadDataWFromLSU),
.DataStall(DataStall),
.*);
lsu lsu(.MemRWM(MemRWMtoLSU),
.Funct3M(Funct3MtoLSU),
.AtomicM(AtomicMtoLSU),
.MemAdrM(MemAdrMtoLSU),
.WriteDataM(WriteDataMtoLSU),
.ReadDataW(ReadDataWFromLSU),
.CommittedM(CommittedMfromLSU),
.SquashSCW(SquashSCWfromLSU),
.DataMisalignedM(DataMisalignedMfromLSU),
.DisableTranslation(DisableTranslation),
.DataStall(DataStall), .* ); // data cache unit
ahblite ebu( ahblite ebu(
//.InstrReadF(1'b0), //.InstrReadF(1'b0),