forked from Github_Repos/cvw
Missed the force on uart for no tracking.
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parent
56bea58a3c
commit
adb4e30c45
@ -27,7 +27,7 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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`define DEBUG_TRACE 2
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`define DEBUG_TRACE 0
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// Debug Levels
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// Debug Levels
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// 0: don't check against QEMU
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// 0: don't check against QEMU
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// 1: print disagreements with QEMU, but only halt on PCW disagreements
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// 1: print disagreements with QEMU, but only halt on PCW disagreements
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@ -544,8 +544,10 @@ module testbench;
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// override on special conditions \
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// override on special conditions \
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if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) \
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if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) \
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//$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, InstrCountW-1); \
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//$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, InstrCountW-1); \
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if(!NO_IE_MTIME_CHECKPOINT) \
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force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
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force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
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else \
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else \
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if(!NO_IE_MTIME_CHECKPOINT) \
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release dut.core.ieu.dp.ReadDataM; \
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release dut.core.ieu.dp.ReadDataM; \
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if(textM.substr(0,5) == "rdtime") begin \
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if(textM.substr(0,5) == "rdtime") begin \
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//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
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//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
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