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Revert "Fixed buildroot by adding a second ."

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This reverts commit 8b27c1884e.
This commit is contained in:
slmnemo 2022-06-02 12:43:59 -07:00
parent 65b8d0c32a
commit ad9e85beb9
1 changed files with 12 additions and 1 deletions
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13
pipelined/testbench/testbench-linux.sv
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@ -27,6 +27,15 @@
`include "wally-config.vh" `include "wally-config.vh"
// `define DEBUG_TRACE 0 // *** move this info down below and remove this line if parametrization works
// Debug Levels
// 0: don't check against QEMU
// 1: print disagreements with QEMU, but only halt on PCW disagreements
// 2: halt on any disagreement with QEMU except CSRs
// 3: halt on all disagreements with QEMU
// 4: print memory accesses whenever they happen
// 5: print everything
module testbench; module testbench;
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
/////////////////////////////////// CONFIG //////////////////////////////////// /////////////////////////////////// CONFIG ////////////////////////////////////
@ -54,6 +63,7 @@ module testbench;
//////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////
//////////////////////// SIGNAL / VAR / MACRO DECLARATIONS ///////////////////////// //////////////////////// SIGNAL / VAR / MACRO DECLARATIONS /////////////////////////
//////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////
@ -235,6 +245,7 @@ module testbench;
logic clk, reset_ext; logic clk, reset_ext;
logic reset; logic reset;
initial begin reset_ext <= 1; # 22; reset_ext <= 0; end initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
initial begin $display(DEBUG_TRACE); #1; end // *** remove this once debug trace is parametrized
always begin clk <= 1; # 5; clk <= 0; # 5; end always begin clk <= 1; # 5; clk <= 0; # 5; end
// Wally Interface // Wally Interface
logic [`AHBW-1:0] HRDATAEXT; logic [`AHBW-1:0] HRDATAEXT;
@ -664,7 +675,7 @@ module testbench;
// turn on waves // turn on waves
if (AttemptedInstructionCount == INSTR_WAVEON) $stop; if (AttemptedInstructionCount == INSTR_WAVEON) $stop;
// end sim // end sim
if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) $stop;
fault = 0; fault = 0;
if (DEBUG_TRACE >= 1) begin if (DEBUG_TRACE >= 1) begin
`checkEQ("PCW",PCW,ExpectedPCW) `checkEQ("PCW",PCW,ExpectedPCW)