Commented out some unused modules

wally-pipelined/src/fpu/mult_R4_64_64_cs.sv

@@ -2,6 +2,7 @@
 // It is unsigned and uses Radix-4 Booth encoding.
 // This file was automatically generated by tdm.pl.
 
+/*
 module mult64 (x, y, P);
 
    input [63:0]   x;
@@ -18,7 +19,8 @@ module mult64 (x, y, P);
    //assign P = Pt[127:0];
    ldf128 cpa (cout, P, Sum, Carry, 1'b0);   
 
-endmodule // mult64  
+endmodule // mult64 
+*/ 
 
 module multiplier( y, x, Sum, Carry );
    
@@ -11612,7 +11614,7 @@ module r4be(x0,x1,x2,sing,doub,neg);
    
 endmodule // r4be
 
-
+/*
 // Use maj and two xor2's, with cin being late
 module fullAdd_xc(cout, s, a, b, cin);
    
@@ -11629,7 +11631,7 @@ module fullAdd_xc(cout, s, a, b, cin);
    maj   MAJ_0_112(cout,a,b,cin);
    
 endmodule // fullAdd_xc
-
+*/
 
 module maj(y, a, b, c);
    
@@ -11645,6 +11647,7 @@ module maj(y, a, b, c);
    
 endmodule // maj
 
+/*
 // 4:2 Weinberger compressor
 module fourtwo_x(t, S, C, X, Y, Z, W, t_1);
    
@@ -11664,6 +11667,7 @@ module fourtwo_x(t, S, C, X, Y, Z, W, t_1);
    fullAdd_xc secondCSA_0_160(C,S,W,t_1,intermediate);
    
 endmodule // fourtwo_x
+*/
 
 module inverter(egress, in);
    
@@ -11767,6 +11771,7 @@ module fullAdd_x(cout,sum,a,b,c);
    
 endmodule // fullAdd_x
 
+/*
 module nand2(egress,in1,in2);
 
    output egress;
@@ -11800,7 +11805,7 @@ module and3(y,a,b,c);
    assign y = a&b&c;
 
 endmodule // and3
-
+*/
 module and2(y,a,b);
    
    output y;
@@ -11810,7 +11815,7 @@ module and2(y,a,b);
    assign y = a&b;
 
 endmodule // and2
-
+/*
 module nor2(egress,in1,in2);
 
    output egress;
@@ -11902,6 +11907,7 @@ module oai(egress,in1,in2,in3);
    assign egress = ~(in3 & (in1|in2));      
 
 endmodule // oai
+*/
 
 module aoi(egress,in1,in2,in3);
    
@@ -11949,7 +11955,7 @@ module fullAdd_i(cout_b,sum_b,a,b,c);
    sum_b sum_0_32(sum_b,a,b,c,cout_b);
    
 endmodule // fullAdd_i
-
+/*
 module fullAdd(cout,s,a,b,c);
    
    output cout;
@@ -11979,7 +11985,7 @@ module blackCell(g_i_j, p_i_j, g_i_k, p_i_k, g_kneg1_j, p_kneg1_j);
    and2	 and_0_48(p_i_j, p_i_k, p_kneg1_j);
    
 endmodule // blackCell
-
+*/
 module grayCell(g_i_j, g_i_k, p_i_k, g_kneg1_j);
    
    output g_i_j;

wally-pipelined/src/fpu/shifter_denorm.sv

@@ -118,6 +118,7 @@ module barrel_shifter_r57 (Z, Sticky, A, Shift);
 
 endmodule // barrel_shifter_r57
 
+/*
 module barrel_shifter_r64 (Z, Sticky, A, Shift);
    
    input [63:0] A;
@@ -160,3 +161,4 @@ module barrel_shifter_r64 (Z, Sticky, A, Shift);
    assign Sticky = (S != sixtythreezeros);
 
 endmodule // barrel_shifter_r64
+*/

wally-pipelined/src/muldiv/div.sv

@@ -307,7 +307,7 @@ module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c,
    assign carry = {carry_temp[WIDTH-1:1], 1'b0};     
 
 endmodule // csa
-
+/*
 module eqcmp #(parameter WIDTH = 8)
    (input  logic [WIDTH-1:0] a, b,
     output logic y);
@@ -315,6 +315,7 @@ module eqcmp #(parameter WIDTH = 8)
    assign y = (a == b);
    
 endmodule // eqcmp
+*/
 
 // QST for r=4
 module qst4 (input logic [6:0] s, input logic [2:0] d,

wally-pipelined/src/uncore/imem.sv

@@ -1,71 +0,0 @@
-///////////////////////////////////////////
-// imem.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//
-// Purpose: 
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module imem (
-  input  logic [`XLEN-1:1] AdrF,
-  output logic [31:0]      InstrF,
-  output logic [15:0]      rd2, // bogus, delete when real multicycle fetch works
-  output logic             InstrAccessFaultF);
-
- /* verilator lint_off UNDRIVEN */
-  logic [`XLEN-1:0] RAM[`TIM_BASE>>(1+`XLEN/32):(`TIM_RANGE+`TIM_BASE)>>(1+`XLEN/32)];
-  logic [`XLEN-1:0] bootram[`BOOTTIM_BASE>>(1+`XLEN/32):(`BOOTTIM_RANGE+`BOOTTIM_BASE)>>(1+`XLEN/32)];
- /* verilator lint_on UNDRIVEN */
-  logic [31:0] adrbits; // needs to be 32 bits to index RAM
-  logic [`XLEN-1:0] rd;
-//  logic [15:0] rd2;
-      
-  generate
-    if (`XLEN==32) assign adrbits = AdrF[31:2];
-    else          assign adrbits = AdrF[31:3];
-  endgenerate
-
-  assign #2 rd = (AdrF < (`TIM_BASE >> 1)) ? bootram[adrbits] : RAM[adrbits]; // busybear: 2 memory options
-
-  // hack right now for unaligned 32-bit instructions
-  // eventually this will need to cause a stall like a cache miss
-  // when the instruction wraps around a cache line
-  // could be optimized to only stall when the instruction wrapping is 32 bits
-  assign #2 rd2 = (AdrF < (`TIM_BASE >> 1)) ? bootram[adrbits+1][15:0] : RAM[adrbits+1][15:0]; //busybear: 2 memory options
-  generate 
-    if (`XLEN==32) begin
-      assign InstrF = AdrF[1] ? {rd2[15:0], rd[31:16]} : rd;
-      // First, AdrF needs to get its last bit appended back onto it
-      // Then not-XORing it with TIM_BASE checks if it matches TIM_BASE exactly
-      // Then ORing it with TIM_RANGE introduces some leeway into the previous check, by allowing the lower bits to be either high or low
-
-      assign InstrAccessFaultF = (~&(({AdrF,1'b0} ~^ `TIM_BASE) | `TIM_RANGE)) & (~&(({AdrF,1'b0} ~^ `BOOTTIM_BASE) | `BOOTTIM_RANGE));
-
-    end else begin
-      assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32])
-                          : (AdrF[1] ? rd[47:16] : rd[31:0]);
-      // 
-      assign InstrAccessFaultF = (|AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `TIM_BASE | `TIM_RANGE)) & (|AdrF[`XLEN-1:32] | ~&({AdrF[31:1],1'b0} ~^ `BOOTTIM_BASE | `BOOTTIM_RANGE));
-    end
-  endgenerate
-endmodule
-