forked from Github_Repos/cvw
Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
This commit is contained in:
Kip Macsai-Goren
parent
6bab454b17
commit
ac597d78c8
@ -75,15 +75,15 @@ module ifu (
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output logic ITLBMissF, ITLBHitF,
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// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
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input logic [31:0] HADDR,
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input logic [2:0] HSIZE,
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input logic HWRITE,
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// input logic [31:0] HADDR,
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// input logic [2:0] HSIZE,
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// input logic HWRITE,
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input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so they're gonna have to come over into ifu and dmem
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
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output logic PMPInstrAccessFaultF, PMAInstrAccessFaultF,
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output logic ISquashBusAccessF,
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output logic [5:0] IHSELRegionsF
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output logic ISquashBusAccessF
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// output logic [5:0] IHSELRegionsF
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);
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@ -104,13 +104,17 @@ module ifu (
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logic PMPLoadAccessFaultM, PMPStoreAccessFaultM; // *** these are just so that the mmu has somewhere to put these outputs, they're unused in this stage
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// if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
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logic [`PA_BITS-1:0] PCPFmmu;
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logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
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;
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generate
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if (`XLEN==32)
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if (`XLEN==32) begin
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assign PCPF = PCPFmmu[31:0];
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else
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assign PCNextFPhys = {{(`PA_BITS-`XLEN){1'b0}}, PCNextF};
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end else begin
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assign PCPF = {8'b0, PCPFmmu};
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assign PCNextFPhys = PCNextF[`PA_BITS-1:0];
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end
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endgenerate
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mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1))
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@ -125,12 +129,12 @@ module ifu (
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.TLBMiss(ITLBMissF),
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.TLBHit(ITLBHitF),
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.TLBPageFault(ITLBInstrPageFaultF),
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.ExecuteAccessF(1'b1),
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.InstrReadF(InstrReadF),
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.AtomicAccessM(1'b0),
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.WriteAccessM(1'b0),
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.ReadAccessM(1'b0),
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.MemReadM(1'b0),
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.MemWriteM(1'b0),
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.SquashBusAccess(ISquashBusAccessF),
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.HSELRegions(IHSELRegionsF),
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// .HSELRegions(IHSELRegionsF),
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.DisableTranslation(1'b0),
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.*);
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@ -147,7 +151,7 @@ module ifu (
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// assign InstrReadF = 1; // *** & ICacheMissF; add later
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icache icache(.*,
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.PCNextF(PCNextF[`PA_BITS-1:0]),
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.PCNextF(PCNextFPhys),
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.PCPF(PCPFmmu));
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flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD);
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@ -92,8 +92,8 @@ module lsu (
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output logic PMALoadAccessFaultM, PMAStoreAccessFaultM,
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output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa.
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output logic DSquashBusAccessM,
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output logic [5:0] DHSELRegionsM
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output logic DSquashBusAccessM
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// output logic [5:0] DHSELRegionsM
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);
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@ -127,12 +127,12 @@ module lsu (
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.TLBMiss(DTLBMissM),
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.TLBHit(DTLBHitM),
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.TLBPageFault(DTLBPageFaultM),
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.ExecuteAccessF(1'b0),
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.AtomicAccessM(|AtomicM),
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.WriteAccessM(MemRWM[0]),
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.ReadAccessM(MemRWM[1]),
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.InstrReadF(1'b0),
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.AtomicAccessM(AtomicMaskedM[1]),
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.MemWriteM(MemRWM[0]),
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.MemReadM(MemRWM[1]),
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.SquashBusAccess(DSquashBusAccessM),
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.HSELRegions(DHSELRegionsM),
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// .SelRegions(DHSELRegionsM),
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.*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
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// Specify which type of page fault is occurring
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@ -214,13 +214,13 @@ module lsu (
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else NextState = STATE_READY;
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STATE_FETCH_AMO: if (MemAckW) NextState = STATE_FETCH;
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else NextState = STATE_FETCH_AMO;
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STATE_FETCH: if (MemAckW & ~StallW) NextState = STATE_READY;
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STATE_FETCH: if (MemAckW & ~StallW) NextState = STATE_READY; // StallW will stay high if datastall stays high, so right now, once we get into STATE_FETCH, datastall goes high, and we never leave
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else if (MemAckW & StallW) NextState = STATE_STALLED;
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else NextState = STATE_FETCH;
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STATE_STALLED: if (~StallW) NextState = STATE_READY;
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else NextState = STATE_STALLED;
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default: NextState = STATE_READY;
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endcase // case (CurrState)
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endcase
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end
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endmodule
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@ -26,13 +26,13 @@
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`include "wally-config.vh"
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module adrdec (
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input logic [31:0] HADDR,
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input logic [31:0] Base, Range,
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input logic Supported,
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input logic AccessValid,
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input logic [2:0] Size,
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input logic [3:0] SizeMask,
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output logic HSEL
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input logic [`PA_BITS-1:0] PhysicalAddress,
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input logic [`PA_BITS-1:0] Base, Range,
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input logic Supported,
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input logic AccessValid,
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input logic [1:0] Size,
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input logic [3:0] SizeMask,
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output logic Sel
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);
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logic Match;
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@ -41,12 +41,12 @@ module adrdec (
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// determine if an address is in a range starting at the base
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// for example, if Base = 0x04002000 and range = 0x00000FFF,
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// then anything address between 0x04002000 and 0x04002FFF should match (HSEL=1)
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assign Match = &((HADDR ~^ Base) | Range);
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assign Match = &((PhysicalAddress ~^ Base) | Range);
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// determine if legal size of access is being made (byte, halfword, word, doubleword)
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assign SizeValid = SizeMask[Size[1:0]];
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assign SizeValid = SizeMask[Size];
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assign HSEL = Match && Supported && AccessValid && SizeValid;
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assign Sel = Match && Supported && AccessValid && SizeValid;
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endmodule
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@ -26,19 +26,20 @@
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`include "wally-config.vh"
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module adrdecs (
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input logic [31:0] HADDR, // *** will need to use PAdr in mmu, stick with HADDR in uncore
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input logic AccessRW, AccessRX, AccessRWX,
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input logic [2:0] HSIZE,
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output logic [5:0] HSELRegions
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input logic [`PA_BITS-1:0] PhysicalAddress,
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input logic AccessRW, AccessRX, AccessRWX,
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input logic [1:0] Size,
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output logic [5:0] SelRegions
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);
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// Determine which region of physical memory (if any) is being accessed
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// *** eventually uncomment Access signals
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adrdec boottimdec(HADDR, `BOOTTIM_BASE, `BOOTTIM_RANGE, `BOOTTIM_SUPPORTED, 1'b1/*AccessRX*/, HSIZE, 4'b1111, HSELRegions[5]);
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adrdec timdec(HADDR, `TIM_BASE, `TIM_RANGE, `TIM_SUPPORTED, 1'b1/*AccessRWX*/, HSIZE, 4'b1111, HSELRegions[4]);
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adrdec clintdec(HADDR, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, HSIZE, 4'b1111, HSELRegions[3]);
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adrdec gpiodec(HADDR, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[2]);
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adrdec uartdec(HADDR, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, HSIZE, 4'b0001, HSELRegions[1]);
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adrdec plicdec(HADDR, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, HSIZE, 4'b0100, HSELRegions[0]);
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adrdec boottimdec(PhysicalAddress, `BOOTTIM_BASE, `BOOTTIM_RANGE, `BOOTTIM_SUPPORTED, 1'b1/*AccessRX*/, Size, 4'b1111, SelRegions[5]);
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adrdec timdec(PhysicalAddress, `TIM_BASE, `TIM_RANGE, `TIM_SUPPORTED, 1'b1/*AccessRWX*/, Size, 4'b1111, SelRegions[4]);
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adrdec clintdec(PhysicalAddress, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, Size, 4'b1111, SelRegions[3]);
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adrdec gpiodec(PhysicalAddress, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[2]);
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adrdec uartdec(PhysicalAddress, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[1]);
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adrdec plicdec(PhysicalAddress, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[0]);
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endmodule
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@ -67,17 +67,17 @@ module mmu #(parameter ENTRY_BITS = 3,
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output logic TLBPageFault,
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// PMA checker signals
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input logic [31:0] HADDR,
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input logic [2:0] HSIZE,
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input logic HWRITE,
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input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
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// input logic [31:0] HADDR,
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// input logic [2:0] HSIZE,
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// input logic HWRITE,
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input logic AtomicAccessM, InstrReadF, MemWriteM, MemReadM,
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input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
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output logic SquashBusAccess, // *** send to privileged unit
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output logic PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM,
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output logic PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM,
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output logic [5:0] HSELRegions
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output logic PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM
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// output logic [5:0] SelRegions
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);
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@ -32,17 +32,15 @@ module pmachecker (
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input logic [`PA_BITS-1:0] PhysicalAddress,
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input logic [1:0] Size,
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input logic [31:0] HADDR,
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input logic [2:0] HSIZE,
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// input logic [31:0] HADDR,
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// input logic [2:0] HSIZE,
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// input logic [2:0] HBURST, // *** in AHBlite, HBURST is hardwired to zero for single bursts only allowed. consider removing from this module if unused.
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input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use.
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input logic AtomicAccessM, InstrReadF, MemWriteM, MemReadM, // *** atomicaccessM is unused but might want to stay in for future use.
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output logic Cacheable, Idempotent, AtomicAllowed,
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output logic PMASquashBusAccess,
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output logic [5:0] HSELRegions,
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output logic PMAInstrAccessFaultF,
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output logic PMALoadAccessFaultM,
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output logic PMAStoreAccessFaultM
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@ -51,24 +49,25 @@ module pmachecker (
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// logic BootTim, Tim, CLINT, GPIO, UART, PLIC;
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logic PMAAccessFault;
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logic AccessRW, AccessRWX, AccessRX;
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logic [5:0] SelRegions;
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// Determine what type of access is being made
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assign AccessRW = ReadAccessM | WriteAccessM;
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assign AccessRWX = ReadAccessM | WriteAccessM | ExecuteAccessF;
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assign AccessRX = ReadAccessM | ExecuteAccessF;
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assign AccessRW = MemReadM | MemWriteM;
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assign AccessRWX = MemReadM | MemWriteM | InstrReadF;
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assign AccessRX = MemReadM | InstrReadF;
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// Determine which region of physical memory (if any) is being accessed
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adrdecs adrdecs(HADDR, AccessRW, AccessRX, AccessRWX, HSIZE, HSELRegions);
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adrdecs adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWX, Size, SelRegions);
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// Only RAM memory regions are cacheable
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assign Cacheable = HSELRegions[5] | HSELRegions[4];
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assign Idempotent = HSELRegions[4];
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assign AtomicAllowed = HSELRegions[4];
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assign Cacheable = SelRegions[5] | SelRegions[4];
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assign Idempotent = SelRegions[4];
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assign AtomicAllowed = SelRegions[4];
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// Detect access faults
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assign PMAAccessFault = (~|HSELRegions) && AccessRWX;
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assign PMAInstrAccessFaultF = ExecuteAccessF && PMAAccessFault;
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assign PMALoadAccessFaultM = ReadAccessM && PMAAccessFault;
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assign PMAStoreAccessFaultM = WriteAccessM && PMAAccessFault;
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assign PMAAccessFault = (~|SelRegions) & AccessRWX;
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assign PMAInstrAccessFaultF = InstrReadF & PMAAccessFault;
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assign PMALoadAccessFaultM = MemReadM & PMAAccessFault;
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assign PMAStoreAccessFaultM = MemWriteM & PMAAccessFault;
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assign PMASquashBusAccess = PMAAccessFault;
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endmodule
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@ -30,7 +30,8 @@
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`include "wally-config.vh"
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module pmpadrdec (
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input logic [31:0] HADDR, // *** replace with PAdr
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input logic [`PA_BITS-1:0] PhysicalAddress,
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// input logic [31:0] HADDR, // *** replace with PAdr
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input logic [1:0] AdrMode,
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input logic [`XLEN-1:0] CurrentPMPAdr,
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input logic AdrAtLeastPreviousPMP,
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@ -45,15 +46,15 @@ module pmpadrdec (
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logic TORMatch, NAMatch;
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logic AdrBelowCurrentPMP;
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logic [`PA_BITS-1:0] CurrentAdrFull;
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logic [`PA_BITS-1:0] FakePhysAdr;
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// logic [`PA_BITS-1:0] FakePhysAdr;
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// ***replace this when the true physical address from MMU is available
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assign FakePhysAdr = {{(`PA_BITS-32){1'b0}}, HADDR};
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// assign FakePhysAdr = {{(`PA_BITS-32){1'b0}}, HADDR};
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// Top-of-range (TOR)
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// Append two implicit trailing 0's to PMPAdr value
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assign CurrentAdrFull = {CurrentPMPAdr[`PA_BITS-3:0], 2'b00};
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assign AdrBelowCurrentPMP = /*HADDR */FakePhysAdr < CurrentAdrFull; // *** make sure unsigned comparison works correctly
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assign AdrBelowCurrentPMP = PhysicalAddress < CurrentAdrFull; // *** make sure unsigned comparison works correctly
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assign AdrAtLeastCurrentPMP = ~AdrBelowCurrentPMP;
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assign TORMatch = AdrAtLeastPreviousPMP && AdrBelowCurrentPMP;
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@ -73,7 +74,7 @@ module pmpadrdec (
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endgenerate
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// verilator lint_on UNOPTFLAT
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assign NAMatch = &((FakePhysAdr ~^ CurrentAdrFull) | Mask);
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assign NAMatch = &((PhysicalAddress ~^ CurrentAdrFull) | Mask);
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/* generate
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if (`XLEN == 32 || `XLEN == 64) begin // ***redo for various sizes
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@ -30,8 +30,8 @@
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module pmpchecker (
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// input logic clk, reset, //*** it seems like clk, reset is also not needed here?
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input logic [31:0] HADDR,
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input logic [`PA_BITS-1:0] PhysicalAddress,
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// input logic [31:0] HADDR,
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input logic [1:0] PrivilegeModeW,
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@ -50,7 +50,7 @@ module pmpchecker (
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// we don't have to pass around 16 whole registers.
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
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input logic ExecuteAccessF, WriteAccessM, ReadAccessM,
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input logic InstrReadF, MemWriteM, MemReadM,
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output logic PMPSquashBusAccess,
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@ -84,17 +84,20 @@ module pmpchecker (
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assign {PMPCFG[7], PMPCFG[6], PMPCFG[5], PMPCFG[4],
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PMPCFG[3], PMPCFG[2], PMPCFG[1], PMPCFG[0]} = PMPCFG01_REGW;
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pmpadrdec pmpadrdec(.HADDR(HADDR), .AdrMode(PMPCFG[0][4:3]),
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pmpadrdec pmpadrdec(.PhysicalAddress(PhysicalAddress),
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.AdrMode(PMPCFG[0][4:3]),
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.CurrentPMPAdr(PMPADDR_ARRAY_REGW[0]),
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.AdrAtLeastPreviousPMP(1'b1),
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.AdrAtLeastCurrentPMP(AboveRegion[0]),
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.Match(Regions[0]));
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assign ActiveRegion[0] = |PMPCFG[0][4:3];
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generate // *** only for PMP_ENTRIES > 0
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genvar i;
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for (i = 1; i < `PMP_ENTRIES; i++) begin
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pmpadrdec pmpadrdec(.HADDR(HADDR), .AdrMode(PMPCFG[i][4:3]),
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pmpadrdec pmpadrdec(.PhysicalAddress(PhysicalAddress),
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.AdrMode(PMPCFG[i][4:3]),
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.CurrentPMPAdr(PMPADDR_ARRAY_REGW[i]),
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.AdrAtLeastPreviousPMP(AboveRegion[i-1]),
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.AdrAtLeastCurrentPMP(AboveRegion[i]),
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@ -131,26 +134,26 @@ module pmpchecker (
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default: MatchedRegion = 0; // Should only occur if there is no match
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endcase
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assign L_Bit = PMPCFG[MatchedRegion][7] && Match;
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assign X_Bit = PMPCFG[MatchedRegion][2] && Match;
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assign W_Bit = PMPCFG[MatchedRegion][1] && Match;
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assign R_Bit = PMPCFG[MatchedRegion][0] && Match;
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assign L_Bit = PMPCFG[MatchedRegion][7] & Match;
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assign X_Bit = PMPCFG[MatchedRegion][2] & Match;
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assign W_Bit = PMPCFG[MatchedRegion][1] & Match;
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assign R_Bit = PMPCFG[MatchedRegion][0] & Match;
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assign InvalidExecute = ExecuteAccessF && ~X_Bit;
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assign InvalidWrite = WriteAccessM && ~W_Bit;
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assign InvalidRead = ReadAccessM && ~R_Bit;
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assign InvalidExecute = InstrReadF & ~X_Bit;
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assign InvalidWrite = MemWriteM & ~W_Bit;
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assign InvalidRead = MemReadM & ~R_Bit;
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// *** don't cause faults when there are no PMPs
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assign PMPInstrAccessFaultF = (PrivilegeModeW == `M_MODE) ?
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Match && L_Bit && InvalidExecute :
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EnforcePMP && InvalidExecute;
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Match & L_Bit & InvalidExecute :
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EnforcePMP & InvalidExecute;
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assign PMPStoreAccessFaultM = (PrivilegeModeW == `M_MODE) ?
|
||||
Match && L_Bit && InvalidWrite :
|
||||
EnforcePMP && InvalidWrite;
|
||||
Match & L_Bit & InvalidWrite :
|
||||
EnforcePMP & InvalidWrite;
|
||||
assign PMPLoadAccessFaultM = (PrivilegeModeW == `M_MODE) ?
|
||||
Match && L_Bit && InvalidRead :
|
||||
EnforcePMP && InvalidRead;
|
||||
Match & L_Bit & InvalidRead :
|
||||
EnforcePMP & InvalidRead;
|
||||
|
||||
assign PMPSquashBusAccess = PMPInstrAccessFaultF || PMPLoadAccessFaultM || PMPStoreAccessFaultM;
|
||||
assign PMPSquashBusAccess = PMPInstrAccessFaultF | PMPLoadAccessFaultM | PMPStoreAccessFaultM;
|
||||
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user