Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported

wally-pipelined/src/fpu/fpu.sv

@@ -43,6 +43,10 @@ module fpu (
   output logic [4:0] 	   SetFflagsM,       // FPU flags
   output logic [`XLEN-1:0] FPUResultW);      // FPU result
 // *** change FMA to do 16 - 32 - 64 - 128 FEXPBITS 
+
+  /*generate
+     if (`F_SUPPORTED) begin */
+        
       // control logic signal instantiation
       logic 		   FWriteEnD, FWriteEnE, FWriteEnM, FWriteEnW;              // FP register write enable
       logic [2:0] 	FrmD, FrmE, FrmM;                                  // FP rounding mode
@@ -362,7 +366,7 @@ module fpu (
 
 
 
-//***turn into muxs
+   //***turn into muxs
       always_comb begin
          case (FResultSelW)
       3'b000 : FPUFlagsW = 5'b0;
@@ -392,11 +396,25 @@ module fpu (
       // define offsets for LSB zero extension or truncation
       always_comb begin      
          // zero extension 
-//***turn into mux
+   //***turn into mux
          FPUResultW = FmtW ? FPUResult64W[63:64-`XLEN] : {{`XLEN-32{1'b0}}, FPUResult64W[63:32]};
          //*** put into mem stage
          SetFflagsM = FPUFlagsW;      
       end
 
+   /* end else begin
+     assign FStallD = 0;
+     assign FWriteIntE = 0; 
+     assign FWriteIntM = 0;
+     assign FWriteIntW = 0;
+     assign FWriteDataE = 0;
+     assign FIntResM = 0;
+     assign FDivBusyE = 0;
+     assign IllegalFPUInstrD = 0;
+     assign SetFflagsM = 0;
+     assign FPUResultW = 0;
+   end
+  endgenerate*/
+  
 endmodule // fpu
 

wally-pipelined/src/muldiv/muldiv.sv

@@ -139,6 +139,8 @@ module muldiv (
 
       end else begin // no M instructions supported
 	 	assign MulDivResultW = 0; 
+		assign DivBusyE = 0;
+		assign DivDoneE = 0;
       end
    endgenerate