Merged ALUOp into ALUControl to simplify ALU mux

src/ieu/alu.sv

@@ -86,9 +86,8 @@ module alu #(parameter WIDTH=32) (
  
   // Select appropriate ALU Result
   always_comb begin
-    if (~ALUOp) FullResult = Sum;                         // Always add for ALUOp = 0 (address generation)
+    case (ALUSelect)                                
-    else casez (ALUSelect)                                // Otherwise check Funct3 NOTE: change signal name to ALUSelect
+      3'b000: FullResult = Sum;                           // add or sub (including address generation)
-      3'b000: FullResult = Sum;                           // add or sub
       3'b001: FullResult = Shift;                         // sll, sra, or srl
       3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT};       // slt
       3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU};      // sltu

src/ieu/bmu/bitmanipalu.sv

@@ -62,11 +62,10 @@ module bitmanipalu #(parameter WIDTH=32) (
 
   // Mask Generation Mux
   if (`ZBS_SUPPORTED) begin: zbsdec
-    decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB);
+    decoder #($clog2(WIDTH)) maskgen(B[$clog2(WIDTH)-1:0], MaskB);
     mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB);
   end else assign CondMaskB = B;
  
-    
   // 0-3 bit Pre-Shift Mux
   if (`ZBA_SUPPORTED) begin: zbapreshift
     assign PreShiftAmt = Funct3[2:1] & {2{PreShift}};

src/ieu/bmu/bmuctrl.sv

@@ -34,12 +34,12 @@ module bmuctrl(
   // Decode stage control signals
   input  logic        StallD, FlushD,          // Stall, flush Decode stage
   input  logic [31:0] InstrD,                  // Instruction in Decode stage
+  input  logic        ALUOpD,                  // Regular ALU Operation
   output logic [1:0]  BSelectD,                // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage
   output logic [2:0]  ZBBSelectD,              // ZBB mux select signal in Decode stage NOTE: do we need this in decode?
   output logic        BRegWriteD,              // Indicates if it is a R type B instruction in Decode Stage
   output logic        BALUSrcBD,               // Indicates if it is an I/IW (non auipc) type B instruction in Decode Stage
   output logic        BW64D,                   // Indiciates if it is a W type B instruction in Decode Stage
-  output logic        BALUOpD,                 // Indicates if it is an ALU B instruction in Decode Stage
   output logic        BSubArithD,              // TRUE if ext, clr, andn, orn, xnor instruction in Decode Stage
   output logic        IllegalBitmanipInstrD,   // Indicates if it is unrecognized B instruction in Decode Stage
   // Execute stage control signals             
@@ -61,10 +61,10 @@ module bmuctrl(
   logic       MaskD;                           // Indicates if zbs instruction in Decode Stage
   logic       PreShiftD;                       // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage
   logic [2:0] BALUControlD;                    // ALU Control signals for B instructions
-  logic [2:0] ALUSelectD;                      // ALU Mux select signal in Decode Stage
+  logic [2:0] BALUSelectD, ALUSelectD;         // ALU Mux select signal in Decode Stage
+  logic       BALUOpD;                         // Indicates if it is an ALU B instruction in Decode Stage
 
   `define BMUCTRLW 17
-  `define BMUCTRLWSUB3 14
 
   logic [`BMUCTRLW-1:0] BMUControlsD;                 // Main B Instructions Decoder control signals
 
@@ -76,8 +76,8 @@ module bmuctrl(
 
   // Main Instruction Decoder
   always_comb begin
-    // ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD
+    // BALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD
-    BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1};  // default: Illegal instruction
+    BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1;  // default: Illegal bmu instruction;
     if (`ZBA_SUPPORTED) begin
       casez({OpD, Funct7D, Funct3D})
         17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0;  // sh1add
@@ -157,7 +157,7 @@ module bmuctrl(
           17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0;  // bseti (rv64)
         endcase
     end
-    if (`ZBB_SUPPORTED | `ZBS_SUPPORTED) // rv32i/64i shift instructions need certain BMU shifter control when BMU shifter is used
+    if (`ZBB_SUPPORTED | `ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used
       casez({OpD, Funct7D, Funct3D})
         17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0;  // sra, srl, sll
         17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0;  // srai, srli, slli
@@ -167,7 +167,7 @@ module bmuctrl(
   end
 
   // Unpack Control Signals
-  assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD,BALUSrcBD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD;
+  assign {BALUSelectD, BSelectD, ZBBSelectD, BRegWriteD,BALUSrcBD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD;
   
   // Pack BALUControl Signals
   assign BALUControlD = {RotateD, MaskD, PreShiftD};
@@ -175,6 +175,9 @@ module bmuctrl(
   // Comparator should perform signed comparison when min/max instruction. We have overlap in funct3 with some branch instructions so we use opcode to differentiate betwen min/max and branches
   assign BComparatorSignedD = (Funct3D[2]^Funct3D[0]) & ~OpD[6];
 
+  // Choose ALUSelect brom BMU for BMU operations, Funct3 for IEU operations, or 0 for addition
+  assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000);
+
   // BMU Execute stage pipieline control register
   flopenrc#(13) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD,  BALUControlD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE});
 endmodule

src/ieu/controller.sv

@@ -127,7 +127,6 @@ module controller(
   logic [2:0]  ZBBSelectD;                     // ZBB Mux Select Signal
   logic        BRegWriteD;                     // Indicates if it is a R type B instruction in decode stage
   logic        BW64D;                          // Indicates if it is a W type B instruction in decode stage
-  logic        BALUOpD;                        // Indicates if it is an ALU B instruction in decode stage
   logic        BSubArithD;                     // TRUE for B-type ext, clr, andn, orn, xnor
   logic        BALUSrcBD;                      // B-type alu src select signal
   logic        BComparatorSignedE;             // Indicates if max, min (signed comarison) instruction in Execute Stage
@@ -235,11 +234,10 @@ module controller(
   assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; //NOTE: Do we want to segregate the IllegalBitmanipInstrD into its own output signal
   //assign IllegalBaseInstrD = 1'b0;
   assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD,
-          ResultSrcD, BranchD, BaseALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, 
+          ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, 
           PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD;
 
   // If either bitmanip signal or base instruction signal
-  assign ALUOpD = BaseALUOpD | BALUOpD; 
   assign RegWriteD = BaseRegWriteD | BRegWriteD; 
   assign W64D = BaseW64D | BW64D;
   assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD;
@@ -259,8 +257,8 @@ module controller(
 
   // bit manipulation Configuration Block
   if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
-    bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .BSelectD, .ZBBSelectD, 
+    bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUOpD, .BSelectD, .ZBBSelectD, 
-      .BRegWriteD, .BALUSrcBD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, 
+      .BRegWriteD, .BALUSrcBD, .BW64D, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, 
       .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE);
     if (`ZBA_SUPPORTED) begin
       // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw
@@ -274,7 +272,6 @@ module controller(
     assign ZBBSelectE = 3'b000;
     assign BRegWriteD = 1'b0;
     assign BW64D = 1'b0;
-    assign BALUOpD = 1'b0;
     assign BRegWriteE = 1'b0;
     assign BSubArithD = 1'b0;
     assign BComparatorSignedE = 1'b0;