Merge small mmu changes into main

This commit is contained in:
Kip Macsai-Goren 2021-06-08 14:00:26 -04:00
commit aab7bd94f7
9 changed files with 22 additions and 27 deletions

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@ -96,7 +96,7 @@ module dmem (
// *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM), mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM),
.PageTableEntryWrite(PageTableEntryM), .PageTypeWrite(PageTypeM), .PTEWriteVal(PageTableEntryM), .PageTypeWriteVal(PageTypeM),
.TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM), .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM),
.PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM), .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM),
.TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM), .TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM),

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@ -105,7 +105,7 @@ module ifu (
// if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. // if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF), mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF),
.PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF), .PTEWriteVal(PageTableEntryF), .PageTypeWriteVal(PageTypeF),
.TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF), .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF),
.PhysicalAddress(PCPF), .TLBMiss(ITLBMissF), .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF),
.TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF), .TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF),

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@ -33,14 +33,14 @@ module camline #(parameter KEY_BITS = 20,
input logic clk, reset, input logic clk, reset,
// input to check which SvMode is running // input to check which SvMode is running
input logic [`SVMODE_BITS-1:0] SvMode, // input logic [`SVMODE_BITS-1:0] SvMode, // *** may no longer be needed.
// The requested page number to compare against the key // The requested page number to compare against the key
input logic [KEY_BITS-1:0] VirtualPageNumber, input logic [KEY_BITS-1:0] VirtualPageNumber,
// Signals to write a new entry to this line // Signals to write a new entry to this line
input logic CAMLineWrite, input logic CAMLineWrite,
input logic [1:0] PageTypeWrite, input logic [1:0] PageTypeWriteVal,
// Flush this line (set valid to 0) // Flush this line (set valid to 0)
input logic TLBFlush, input logic TLBFlush,
@ -96,13 +96,8 @@ module camline #(parameter KEY_BITS = 20,
end end
endgenerate endgenerate
// When determining a match for a superpage, we might use only a portion of
// the input VirtualPageNumber. Unused parts of the VirtualPageNumber are
// zeroed in VirtualPageNumberQuery to better match with Key.
logic [KEY_BITS-1:0] VirtualPageNumberQuery;
// On a write, update the type of the page referred to by this line. // On a write, update the type of the page referred to by this line.
flopenr #(2) pagetypeflop(clk, reset, CAMLineWrite, PageTypeWrite, PageType); flopenr #(2) pagetypeflop(clk, reset, CAMLineWrite, PageTypeWriteVal, PageType);
//mux2 #(2) pagetypemux(StoredPageType, PageTypeWrite, CAMLineWrite, PageType); //mux2 #(2) pagetypemux(StoredPageType, PageTypeWrite, CAMLineWrite, PageType);
// On a write, set the valid bit high and update the stored key. // On a write, set the valid bit high and update the stored key.

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@ -49,8 +49,8 @@ module mmu #(parameter ENTRY_BITS = 3,
input logic [`XLEN-1:0] VirtualAddress, input logic [`XLEN-1:0] VirtualAddress,
// Controls for writing a new entry to the TLB // Controls for writing a new entry to the TLB
input logic [`XLEN-1:0] PageTableEntryWrite, input logic [`XLEN-1:0] PTEWriteVal,
input logic [1:0] PageTypeWrite, input logic [1:0] PageTypeWriteVal,
input logic TLBWrite, input logic TLBWrite,
// Invalidate all TLB entries // Invalidate all TLB entries

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@ -28,13 +28,13 @@
`include "wally-config.vh" `include "wally-config.vh"
module pmachecker ( module pmachecker (
input logic clk, reset, // input logic clk, reset, // *** unused in this module and all sub modules.
input logic [31:0] HADDR, input logic [31:0] HADDR,
input logic [2:0] HSIZE, input logic [2:0] HSIZE,
input logic [2:0] HBURST, // input logic [2:0] HBURST, // *** in AHBlite, HBURST is hardwired to zero for single bursts only allowed. consider removing from this module if unused.
input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use.
output logic Cacheable, Idempotent, AtomicAllowed, output logic Cacheable, Idempotent, AtomicAllowed,
output logic PMASquashBusAccess, output logic PMASquashBusAccess,
@ -92,7 +92,7 @@ module pmachecker (
endmodule endmodule
module attributes ( module attributes (
input logic clk, reset, // input logic clk, reset, // *** unused in this module and all sub modules.
input logic [31:0] Address, input logic [31:0] Address,

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@ -29,7 +29,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module pmpchecker ( module pmpchecker (
input logic clk, reset, // input logic clk, reset, //*** it seems like clk, reset is also not needed here?
input logic [31:0] HADDR, input logic [31:0] HADDR,

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@ -70,8 +70,8 @@ module tlb #(parameter ENTRY_BITS = 3,
input logic [`XLEN-1:0] VirtualAddress, input logic [`XLEN-1:0] VirtualAddress,
// Controls for writing a new entry to the TLB // Controls for writing a new entry to the TLB
input logic [`XLEN-1:0] PageTableEntryWrite, input logic [`XLEN-1:0] PTEWriteVal,
input logic [1:0] PageTypeWrite, input logic [1:0] PageTypeWriteVal,
input logic TLBWrite, input logic TLBWrite,
// Invalidate all TLB entries // Invalidate all TLB entries
@ -94,7 +94,7 @@ module tlb #(parameter ENTRY_BITS = 3,
// Index (currently random) to write the next TLB entry // Index (currently random) to write the next TLB entry
logic [ENTRY_BITS-1:0] WriteIndex; logic [ENTRY_BITS-1:0] WriteIndex;
logic [2**ENTRY_BITS-1:0] WriteLines; // used as the one-hot encoding of WriteIndex logic [(2**ENTRY_BITS)-1:0] WriteLines; // used as the one-hot encoding of WriteIndex
// Sections of the virtual and physical addresses // Sections of the virtual and physical addresses
logic [`VPN_BITS-1:0] VirtualPageNumber; logic [`VPN_BITS-1:0] VirtualPageNumber;
@ -119,7 +119,7 @@ module tlb #(parameter ENTRY_BITS = 3,
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
// Decode the integer encoded WriteIndex into the one-hot encoded WriteLines // Decode the integer encoded WriteIndex into the one-hot encoded WriteLines
decoder writedecoder(WriteIndex, WriteLines); decoder #(ENTRY_BITS) writedecoder(WriteIndex, WriteLines);
// The bus width is always the largest it could be for that XLEN. For example, vpn will be 36 bits wide in rv64 // The bus width is always the largest it could be for that XLEN. For example, vpn will be 36 bits wide in rv64
// this, even though it could be 27 bits (SV39) or 36 bits (SV48) wide. When the value of VPN is narrower, // this, even though it could be 27 bits (SV39) or 36 bits (SV48) wide. When the value of VPN is narrower,

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@ -33,8 +33,8 @@ module tlbcam #(parameter ENTRY_BITS = 3,
parameter SEGMENT_BITS = 10) ( parameter SEGMENT_BITS = 10) (
input logic clk, reset, input logic clk, reset,
input logic [KEY_BITS-1:0] VirtualPageNumber, input logic [KEY_BITS-1:0] VirtualPageNumber,
input logic [1:0] PageTypeWrite, input logic [1:0] PageTypeWriteVal,
input logic [`SVMODE_BITS-1:0] SvMode, // input logic [`SVMODE_BITS-1:0] SvMode, // *** may not need to be used.
input logic TLBWrite, input logic TLBWrite,
input logic TLBFlush, input logic TLBFlush,
input logic [2**ENTRY_BITS-1:0] WriteLines, input logic [2**ENTRY_BITS-1:0] WriteLines,
@ -69,7 +69,7 @@ module tlbcam #(parameter ENTRY_BITS = 3,
// In case there are multiple matches in the CAM, select only one // In case there are multiple matches in the CAM, select only one
// *** it might be guaranteed that the CAM will never have multiple matches. // *** it might be guaranteed that the CAM will never have multiple matches.
// If so, this is just an encoder // If so, this is just an encoder
priorityencoder #(ENTRY_BITS) matchpriority(Matches, VPNIndex); priorityencoder #(ENTRY_BITS) matchencoder(Matches, VPNIndex);
assign CAMHit = |Matches & ~TLBFlush; assign CAMHit = |Matches & ~TLBFlush;
assign HitPageType = PageTypeList[VPNIndex]; assign HitPageType = PageTypeList[VPNIndex];

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@ -30,8 +30,8 @@
module tlbram #(parameter ENTRY_BITS = 3) ( module tlbram #(parameter ENTRY_BITS = 3) (
input logic clk, reset, input logic clk, reset,
input logic [ENTRY_BITS-1:0] VPNIndex, // Index to read from input logic [ENTRY_BITS-1:0] VPNIndex, // Index to read from
input logic [ENTRY_BITS-1:0] WriteIndex, // input logic [ENTRY_BITS-1:0] WriteIndex, // *** unused?
input logic [`XLEN-1:0] PageTableEntryWrite, input logic [`XLEN-1:0] PTEWriteVal,
input logic TLBWrite, input logic TLBWrite,
input logic [2**ENTRY_BITS-1:0] WriteLines, input logic [2**ENTRY_BITS-1:0] WriteLines,
@ -49,7 +49,7 @@ module tlbram #(parameter ENTRY_BITS = 3) (
genvar i; genvar i;
for (i = 0; i < NENTRIES; i++) begin: tlb_ram_flops for (i = 0; i < NENTRIES; i++) begin: tlb_ram_flops
flopenr #(`XLEN) pteflop(clk, reset, WriteLines[i] & TLBWrite, flopenr #(`XLEN) pteflop(clk, reset, WriteLines[i] & TLBWrite,
PageTableEntryWrite, ram[i]); PTEWriteVal, ram[i]);
end end
endgenerate endgenerate