forked from Github_Repos/cvw
Added vm64check tests to cover IMMU vm64
This commit is contained in:
David Harris
parent
25f394ce97
commit
a9b7bd101e
@ -49,7 +49,9 @@ string tvpaths[] = '{
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"csrwrites",
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"priv",
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"ifu",
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"fpu"
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"fpu",
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"lsu",
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"vm64check"
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};
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string coremark[] = '{
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@ -1052,6 +1054,28 @@ string imperas32f[] = '{
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string arch64f[] = '{
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`RISCVARCHTEST,
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"rv64i_m/F/src/fdiv_b1-01.S",
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"rv64i_m/F/src/fdiv_b20-01.S",
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"rv64i_m/F/src/fdiv_b2-01.S",
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"rv64i_m/F/src/fdiv_b21-01.S",
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"rv64i_m/F/src/fdiv_b3-01.S",
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"rv64i_m/F/src/fdiv_b4-01.S",
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"rv64i_m/F/src/fdiv_b5-01.S",
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"rv64i_m/F/src/fdiv_b6-01.S",
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"rv64i_m/F/src/fdiv_b7-01.S",
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"rv64i_m/F/src/fdiv_b8-01.S",
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"rv64i_m/F/src/fdiv_b9-01.S",
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"rv64i_m/F/src/fsqrt_b1-01.S",
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"rv64i_m/F/src/fsqrt_b20-01.S",
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"rv64i_m/F/src/fsqrt_b2-01.S",
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"rv64i_m/F/src/fsqrt_b3-01.S",
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"rv64i_m/F/src/fsqrt_b4-01.S",
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"rv64i_m/F/src/fsqrt_b5-01.S",
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"rv64i_m/F/src/fsqrt_b7-01.S",
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"rv64i_m/F/src/fsqrt_b8-01.S",
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"rv64i_m/F/src/fsqrt_b9-01.S",
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"rv64i_m/F/src/fadd_b10-01.S",
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"rv64i_m/F/src/fadd_b1-01.S",
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"rv64i_m/F/src/fadd_b11-01.S",
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@ -1203,6 +1227,28 @@ string imperas32f[] = '{
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string arch64d[] = '{
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`RISCVARCHTEST,
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// for speed
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"rv64i_m/D/src/fdiv.d_b1-01.S",
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"rv64i_m/D/src/fdiv.d_b20-01.S",
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"rv64i_m/D/src/fdiv.d_b2-01.S",
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"rv64i_m/D/src/fdiv.d_b21-01.S",
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"rv64i_m/D/src/fdiv.d_b3-01.S",
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"rv64i_m/D/src/fdiv.d_b4-01.S",
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"rv64i_m/D/src/fdiv.d_b5-01.S",
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"rv64i_m/D/src/fdiv.d_b6-01.S",
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"rv64i_m/D/src/fdiv.d_b7-01.S",
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"rv64i_m/D/src/fdiv.d_b8-01.S",
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"rv64i_m/D/src/fdiv.d_b9-01.S",
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"rv64i_m/D/src/fsqrt.d_b1-01.S",
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"rv64i_m/D/src/fsqrt.d_b20-01.S",
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"rv64i_m/D/src/fsqrt.d_b2-01.S",
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"rv64i_m/D/src/fsqrt.d_b3-01.S",
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"rv64i_m/D/src/fsqrt.d_b4-01.S",
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"rv64i_m/D/src/fsqrt.d_b5-01.S",
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"rv64i_m/D/src/fsqrt.d_b7-01.S",
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"rv64i_m/D/src/fsqrt.d_b8-01.S",
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"rv64i_m/D/src/fsqrt.d_b9-01.S",
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"rv64i_m/D/src/fadd.d_b10-01.S",
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"rv64i_m/D/src/fadd.d_b1-01.S",
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"rv64i_m/D/src/fadd.d_b11-01.S",
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173
tests/coverage/vm64check.S
Normal file
173
tests/coverage/vm64check.S
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@ -0,0 +1,173 @@
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///////////////////////////////////////////
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// vm64check.S
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//
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// Written: David_Harris@hmc.edu 7 April 2023
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//
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// Purpose: vm64check coverage
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Cover IMMU vm64check block by jumping to illegal virtual addresses
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// Need a nonstandard trap handler to deal with returns from theses jumps
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// assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]);
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// assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]);
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// assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47;
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.section .text.init
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.global rvtest_entry_point
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rvtest_entry_point:
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la sp, topofstack # Initialize stack pointer (not used)
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# Set up interrupts
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la t0, trap_handler
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csrw mtvec, t0 # Initialize MTVEC to trap_handler
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# set up PMP so user and supervisor mode can access full address space
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csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX
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li t0, 0xFFFFFFFF
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csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
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# SATP in non-39 mode
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csrw satp, zero
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// vm64check coverage
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check1:
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// check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal
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li t0, 0x00000001800F0000 # unimplemented memory with upper and lower all zero
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la ra, check2
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jalr t0
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check2:
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li t0, 0xFFFFFFF1800F0000 # unimplemented memory with upper and lower all one
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la ra, check3
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jalr t0
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check3:
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li t0, 0xFFF81001800F0000 # unimplemented memory with upper all one, lower mixed
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la ra, check4
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jalr t0
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check4:
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li t0, 0x03001001800F0000 # unimplemented memory with upper mixed, lower mixed
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la ra, check5
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jalr t0
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check5:
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li t0, 0x00001001800F0000 # unimplemented memory with upper all zero, lower mixed
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la ra, check11
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jalr t0
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check11:
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# SATP in SV39 mode
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li t0, 0x8000000000000000
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csrw satp, t0
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// check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal
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li t0, 0x00000001800F0000 # unimplemented memory with upper and lower all zero
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la ra, check12
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jalr t0
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check12:
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li t0, 0xFFFFFFF1800F0000 # unimplemented memory with upper and lower all one
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la ra, check13
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jalr t0
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check13:
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li t0, 0xFFF81001800F0000 # unimplemented memory with upper all one, lower mixed
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la ra, check14
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jalr t0
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check14:
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li t0, 0x03001001800F0000 # unimplemented memory with upper mixed, lower mixed
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la ra, check15
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jalr t0
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check15:
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li t0, 0x00001001800F0000 # unimplemented memory with upper all zero, lower mixed
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la ra, check16
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jalr t0
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check16:
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write_tohost:
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la t1, tohost
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li t0, 1 # 1 for success, 3 for failure
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sd t0, 0(t1) # send success code
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self_loop:
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j self_loop # wait
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.align 4 # trap handlers must be aligned to multiple of 4
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trap_handler:
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csrw mepc, ra # return to address in ra
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mret
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.section .tohost
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tohost: # write to HTIF
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.dword 0
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fromhost:
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.dword 0
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# Initialize stack with room for 512 bytes
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.bss
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.space 512
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topofstack:
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j done
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lw t1, 0(t0)
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li t0, 0xFFFFFFFF80000000
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lw t1, 0(t0)
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li t1, 0xFFF8000080000000
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lw t1, 0(t0)
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li t1, 0x1000000080000000
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lw t1, 0(t0)
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li t1, 0x0000010080000000
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lw t1, 0(t0)
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li t0, 0x8000000000000000
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csrw satp, t0 # SV39 mode
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li t0, 0x0000000080000000
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lw t1, 0(t0)
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li t0, 0xFFFFFFFF80000000
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lw t1, 0(t0)
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li t1, 0xFFF8000080000000
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lw t1, 0(t0)
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li t1, 0x1000000080000000
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lw t1, 0(t0)
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li t1, 0x0000010080000000
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lw t1, 0(t0)
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li t0, 0x9000000000000000
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csrw satp, t0 # SV48 mode
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li t0, 0x0000000080000000
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lw t1, 0(t0)
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li t0, 0xFFFFFFFF80000000
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lw t1, 0(t0)
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li t1, 0xFFF8000080000000
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lw t1, 0(t0)
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li t1, 0x1000000080000000
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lw t1, 0(t0)
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li t1, 0x0000010080000000
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lw t1, 0(t0)
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li t0, 0x0000000000000000
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csrw satp, t0 # disable virtual memory
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