forked from Github_Repos/cvw
Moved IDIV for postproc into generate block
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@ -98,11 +98,14 @@ module fdivsqrtpostproc(
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// Determine if sticky bit is negative // *** look for ways to optimize this. Shift shouldn't be needed.
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// Determine if sticky bit is negative // *** look for ways to optimize this. Shift shouldn't be needed.
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assign Sum = WC + WS;
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assign Sum = WC + WS;
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assign W = $signed(Sum) >>> `LOGR;
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assign NegStickyM = Sum[`DIVb+3];
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assign NegStickyM = W[`DIVb+3];
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assign DM = {4'b0001, D};
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// *** put conditionals on integer division hardware, move to its own module
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assign PreQmM = NegStickyM ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit
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assign QmM = SqrtM ? (PreQmM << 1) : PreQmM;
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if (`IDIV_ON_FPU) begin
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assign W = $signed(Sum) >>> `LOGR;
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assign DM = {4'b0001, D};
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// Integer division: sign handling for div and rem
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// Integer division: sign handling for div and rem
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always_comb
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always_comb
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@ -170,7 +173,5 @@ module fdivsqrtpostproc(
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assign SpecialFPIntDivResultM = BZeroM ? (RemOpM ? ForwardedSrcAM : {(`XLEN){1'b1}}) : PreFPIntDivResultM[`XLEN-1:0]; // special cases
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assign SpecialFPIntDivResultM = BZeroM ? (RemOpM ? ForwardedSrcAM : {(`XLEN){1'b1}}) : PreFPIntDivResultM[`XLEN-1:0]; // special cases
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// *** conditional on RV64
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// *** conditional on RV64
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assign FPIntDivResultM = (W64M ? {{(`XLEN-32){SpecialFPIntDivResultM[31]}}, SpecialFPIntDivResultM[31:0]} : SpecialFPIntDivResultM[`XLEN-1:0]); // Sign extending in case of W64
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assign FPIntDivResultM = (W64M ? {{(`XLEN-32){SpecialFPIntDivResultM[31]}}, SpecialFPIntDivResultM[31:0]} : SpecialFPIntDivResultM[`XLEN-1:0]); // Sign extending in case of W64
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end
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assign PreQmM = NegStickyM ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit
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assign QmM = SqrtM ? (PreQmM << 1) : PreQmM;
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endmodule
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endmodule
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