forked from Github_Repos/cvw
		
	uncore cleanup
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				| @ -38,7 +38,7 @@ | |||||||
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| module uartPC16550D( | module uartPC16550D( | ||||||
| 	// Processor Interface
 | 	// Processor Interface
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| 	input  logic 	      CLK, PRESETn,                   // UART clock and active low reset
 | 	input  logic 	      PCLK, PRESETn,                  // UART clock and active low reset
 | ||||||
| 	input  logic [2:0]  A,                              // address input (8 registers)
 | 	input  logic [2:0]  A,                              // address input (8 registers)
 | ||||||
| 	input  logic [7:0]  Din,                            // 8-bit WriteData
 | 	input  logic [7:0]  Din,                            // 8-bit WriteData
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| 	output logic [7:0]  Dout,                           // 8-bit ReadData
 | 	output logic [7:0]  Dout,                           // 8-bit ReadData
 | ||||||
|  | |||||||
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