forked from Github_Repos/cvw
		
	busybear: ret is only 1 word
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				| @ -130,6 +130,6 @@ add wave /testbench_busybear/InstrWName | ||||
| #set DefaultRadix hexadecimal | ||||
| # | ||||
| #-- Run the Simulation  | ||||
| run 2630 | ||||
| run 2640 | ||||
| #run -all | ||||
| ##quit | ||||
|  | ||||
| @ -158,8 +158,11 @@ module testbench_busybear(); | ||||
|         $stop; | ||||
|       end | ||||
|       // first read instruction
 | ||||
|       scan_file_PC = $fscanf(data_file_PC, "%s %s\n", PCtext, PCtext2); | ||||
|       PCtext = {PCtext, " ", PCtext2}; | ||||
|       scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext); | ||||
|       if (PCtext != "ret") begin | ||||
|         scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2); | ||||
|         PCtext = {PCtext, " ", PCtext2}; | ||||
|       end | ||||
|       scan_file_PC = $fscanf(data_file_PC, "%x\n", InstrF); | ||||
|       // then expected PC value
 | ||||
|       scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected); | ||||
|  | ||||
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