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fdivsqrtfsm cleanup

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This commit is contained in:
David Harris 2022-09-07 06:27:01 -07:00
parent 8438546d52
commit a0abe48ad2
1 changed files with 10 additions and 28 deletions
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36
pipelined/src/fpu/fdivsqrtfsm.sv
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@ -66,29 +66,8 @@ module fdivsqrtfsm(
//logic [$clog2(`DIVLEN/2+3)-1:0] Dur;
logic [`DIVb+3:0] W;
logic SpecialCase;
logic WZeroDelayed, WZeroD; // *** later remove
//flopen #($clog2(`DIVLEN/2+3)) durflop(clk, DivStart, CalcDur, Dur);
assign DivBusy = (state == BUSY & ~DivDone);
// calculate sticky bit
// - there is a chance that a value is subtracted infinitly, resulting in an exact QM result
// this is only a problem on radix 2 (and possibly maximally redundant 4) since minimally redundant
// radix-4 division can't create a QM that continually adds 0's
if (`RADIX == 2) begin
logic [`DIVb+3:0] FZero, FSticky;
logic [`DIVb+2:0] LastK, FirstK;
assign LastK = ({3'b111, LastC} & ~({3'b111, LastC} << 1));
assign FirstK = ({3'b111, FirstC<<1} & ~({3'b111, FirstC<<1} << 1));
assign FZero = SqrtM ? {LastSM[`DIVb], LastSM, 2'b0} | {LastK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
assign FSticky = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
// *** |... for continual -1 is not efficent fix - also only needed for radix-2
assign WZero = ((NextWSN^NextWCN)=={NextWSN[`DIVb+2:0]|NextWCN[`DIVb+2:0], 1'b0})|(((NextWSN+NextWCN+FZero)==0)&qn[`DIVCOPIES-1]);
assign DivSE = |W&~((W+FSticky)==0); //***not efficent fix == and need the & qn *** use next cycle
end else begin
assign WZero = ((NextWSN^NextWCN)=={NextWSN[`DIVb+2:0]|NextWCN[`DIVb+2:0], 1'b0});
assign DivSE = |W;
end
// check for early termination on an exact result. If the result is not exact, the sticky should be set
if (`RADIX == 2) begin
logic [`DIVb+3:0] FZeroD, FSticky;
logic [`DIVb+2:0] LastK, FirstK;
@ -97,14 +76,13 @@ module fdivsqrtfsm(
assign FZeroD = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
assign FSticky = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
// *** |... for continual -1 is not efficent fix - also only needed for radix-2
assign WZeroD = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0})|(((WS+WC+FZeroD)==0)&qn[`DIVCOPIES-1]);
assign WZero = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0})|(((WS+WC+FZeroD)==0)&qn[`DIVCOPIES-1]);
end else begin
assign WZeroD = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0});
assign WZero = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0});
end
assign DivSE = ~WZero;
flopr #(1) WZeroReg(clk, reset | DivStart, WZero, WZeroDelayed);
assign DivDone = (state == DONE) | (WZeroD & (state == BUSY));
// assign DivDone = (state == DONE) | (WZeroDelayed & (state == BUSY));
assign W = WC+WS;
assign NegSticky = W[`DIVb+3];
assign EarlyTermShiftE = step;
@ -129,4 +107,8 @@ module fdivsqrtfsm(
step <= step - 1;
end
end
assign DivDone = (state == DONE) | (WZero & (state == BUSY));
assign DivBusy = (state == BUSY & ~DivDone);
endmodule