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Changed loop variable in CLINT because of error only seen on VLSI

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This commit is contained in:
David Harris 2022-05-03 10:10:28 +00:00
parent 64ba550493
commit 9e47fca2b7
1 changed files with 11 additions and 11 deletions
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22
pipelined/src/uncore/clint.sv
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@ -52,7 +52,7 @@ module clint (
logic initTrans;
(* mark_debug = "true" *) logic [63:0] MTIMECMP;
logic [`XLEN/8-1:0] ByteMaskM;
integer i;
integer i, j;
assign initTrans = HREADY & HSELCLINT & (HTRANS != 2'b00);
// entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data
@ -94,7 +94,7 @@ module clint (
if (entryd == 16'h4000) begin
for(i=0;i<`XLEN/8;i++)
if(ByteMaskM[i])
MTIMECMP[i*8 +: 8] <= HWDATA[i*8 +: 8];
MTIMECMP[i*8 +: 8] <= HWDATA[i*8 +: 8]; // ***dh: this notation isn't in book yet - maybe from Ross
end
end
@ -107,9 +107,9 @@ module clint (
// MTIMECMP is not reset
end else if (memwrite & entryd == 16'hBFF8) begin
// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
for(i=0;i<`XLEN/8;i++)
if(ByteMaskM[i])
MTIME[i*8 +: 8] <= HWDATA[i*8 +: 8];
for(j=0;j<`XLEN/8;j++)
if(ByteMaskM[j])
MTIME[j*8 +: 8] <= HWDATA[j*8 +: 8];
end else MTIME <= MTIME + 1;
end else begin:clint // 32-bit
always @(posedge HCLK) begin
@ -130,13 +130,13 @@ module clint (
end else if (memwrite) begin
if (entryd == 16'h0000) MSIP <= HWDATA[0];
if (entryd == 16'h4000)
for(i=0;i<`XLEN/8;i++)
if(ByteMaskM[i])
MTIMECMP[i*8 +: 8] <= HWDATA[i*8 +: 8];
for(j=0;j<`XLEN/8;j++)
if(ByteMaskM[j])
MTIMECMP[j*8 +: 8] <= HWDATA[j*8 +: 8];
if (entryd == 16'h4004)
for(i=0;i<`XLEN/8;i++)
if(ByteMaskM[i])
MTIMECMP[32 + i*8 +: 8] <= HWDATA[i*8 +: 8];
for(j=0;j<`XLEN/8;j++)
if(ByteMaskM[j])
MTIMECMP[32 + j*8 +: 8] <= HWDATA[j*8 +: 8];
// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
end