Merge pull request #1 from kipmacsaigoren/kkim_alu_new

removed sign-extension muxes in shifter

src/ieu/alu.sv

@@ -54,6 +54,8 @@ module alu #(parameter WIDTH=32) (
   logic             ALUOp;                                                                  // 0 for address generation addition or 1 for regular ALU ops
   logic             Asign, Bsign;                                                           // Sign bits of A, B
   logic             Rotate;
+  logic [WIDTH:0]   shA;                                                                    // XLEN+1 bit input source to shifter
+  logic [WIDTH-1:0] rotA;                                                                    // XLEN bit input source to shifter
 
 
   if (`ZBS_SUPPORTED) begin: zbsdec
@@ -61,19 +63,32 @@ module alu #(parameter WIDTH=32) (
     assign CondMaskB = (BSelect[0]) ? MaskB : B;
   end else assign CondMaskB = B;
 
-  if (`ZBA_SUPPORTED) begin: zbamuxes
-    // Zero Extend Mux
-    if (WIDTH == 64) begin
-      assign CondZextA = (BSelect[3] & (W64)) ? {{(32){1'b0}}, A[31:0]} : A; //NOTE: do we move this mux select logic into the Decode Stage?
-    end else assign CondZextA = A;
 
+  // Sign/Zero extend mux
+  if (WIDTH == 64) begin // rv64 must handle word s/z extensions
+    always_comb 
+      case ({W64, SubArith})
+        2'b00: shA = {{1'b0}, A};
+        2'b01: shA = {A[63], A};
+        2'b10: shA = {{33'b0}, A[31:0]};
+        2'b11: shA = {{33{A[31]}}, A[31:0]};
+      endcase
+  end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; // rv32 does need to handle s/z extensions
+
+  // shifter rotate source select mux
+  if (`ZBB_SUPPORTED) begin
+    if (WIDTH == 64) assign rotA = (W64) ? {A[31:0], A[31:0]} : A;
+    else assign rotA = A; 
+  end else assign rotA = A;
+    
+  if (`ZBA_SUPPORTED) begin: zbamuxes
     // Pre-Shift Mux
     always_comb
       case (Funct3[2:1] & {2{BSelect[3]}})
-        2'b00: CondShiftA = CondZextA;
+        2'b00: CondShiftA = shA[63:0];
-        2'b01: CondShiftA = {CondZextA[WIDTH-2:0],{1'b0}};   // sh1add
+        2'b01: CondShiftA = {shA[WIDTH-2:0],{1'b0}};   // sh1add
-        2'b10: CondShiftA = {CondZextA[WIDTH-3:0],{2'b00}};  // sh2add
+        2'b10: CondShiftA = {shA[WIDTH-3:0],{2'b00}};  // sh2add
-        2'b11: CondShiftA = {CondZextA[WIDTH-4:0],{3'b000}}; // sh3add
+        2'b11: CondShiftA = {shA[WIDTH-4:0],{3'b000}}; // sh3add
       endcase
   end else assign CondShiftA = A;
 
@@ -89,7 +104,7 @@ module alu #(parameter WIDTH=32) (
   assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
   
   // Shifts
-  shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(Rotate));
+  shifternew sh(.shA(shA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate));
 
   // Condition code flags are based on subtraction output Sum = A-B.
   // Overflow occurs when the numbers being subtracted have the opposite sign 

src/ieu/shifternew.sv

@@ -0,0 +1,85 @@
+///////////////////////////////////////////
+// shifter.sv
+//
+// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu
+// Created: 9 January 2021
+// Modified: 6 February 2023
+//
+// Purpose: RISC-V 32/64 bit shifter
+// 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3)
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module shifternew (
+  input  logic [`XLEN:0]     shA,                           // shift Source
+  input  logic [`XLEN-1:0]   rotA,                          // rotate source
+  input  logic [`LOG_XLEN-1:0] Amt,                         // Shift amount
+  input  logic                 Right, Rotate, W64,          // Shift right, rotate signals
+  output logic [`XLEN-1:0]     Y);                          // Shifted result
+
+  logic [2*`XLEN-2:0]      z, zshift;                       // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
+  logic [`LOG_XLEN-1:0]    amttrunc, offset;                // Shift amount adjusted for RV64, right-shift amount
+
+
+  if (`ZBB_SUPPORTED) begin: rotfunnel
+    if (`XLEN==32) begin // rv32 with rotates
+      always_comb  // funnel mux
+        case({Right, Rotate})
+          2'b00: z = {shA[31:0], 31'b0};
+          2'b01: z = {rotA,rotA[31:1]};
+          2'b10: z = {{31{shA[32]}}, shA[31:0]};
+          2'b11: z = {rotA[30:0],rotA};
+        endcase
+      assign amttrunc = Amt; // shift amount
+    end else begin // rv64 with rotates
+      always_comb  // funnel mux
+        case ({Right, Rotate})
+          2'b00: z = {shA[63:0],{63'b0}};
+          2'b01: z = {rotA, rotA[63:1]};
+          2'b10: z = {{63{shA[64]}},shA[63:0]};
+          2'b11: z = {rotA[62:0],rotA[63:0]};
+        endcase
+      assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift
+    end
+  end else begin: norotfunnel
+    if (`XLEN==32) begin:shifter // RV32
+      always_comb  // funnel mux
+        if (Right)  z = {{31{shA[32]}}, shA[31:0]};
+        else        z = {shA[31:0], 31'b0};
+      assign amttrunc = Amt; // shift amount
+    end else begin:shifter  // RV64
+      always_comb  // funnel mux
+        if (Right)  z = {{63{shA[64]}},shA[63:0]};
+        else        z = {shA[63:0],{63'b0}};
+      assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift
+    end
+  end
+  
+  // Opposite offset for right shifts
+  assign offset = Right ? amttrunc : ~amttrunc;
+  
+  // Funnel operation
+  assign zshift = z >> offset;
+  assign Y = zshift[`XLEN-1:0];    
+endmodule
+
+